Soo-Min Lee
According to our database1,
Soo-Min Lee
authored at least 15 papers
between 2010 and 2024.
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Bibliography
2024
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
IEEE J. Solid State Circuits, January, 2024
2023
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2020
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2017
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
2013
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.
IEEE J. Solid State Circuits, 2012
2011
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010