A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. - Hae-Kang Jung; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. - Hyung-Joon Chi; Young-Ho Choi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park; Jong-Jin Lim; Pil-Sung Kang; Bu-Yeol Lee; Jin-Cheol Hong; Hee-Sub Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. - Hae-Kang Jung; Il-Min Yi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2012)

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. - Soo-Min Lee; Jong-Hoon Kim; Jong-Sam Kim; Yunsaing Kim; Hyunbae Lee; Jae-Yoon Sim; Hong-June Park (ISSCC, 2013)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. - Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young Jae Jang; Hae-Kang Jung; Kyunghoon Kim; Dae-Han Kwon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. - Soo-Min Lee; Jihun Oh; Jinho Choi; Seokkyun Ko; Daero Kim; Kyounghoi Koo; JongRyun Choi; Yoonjee Nam; Sangsoo Park; Hyungkweon Lee; Eunsu Kim; Sukhyun Jung; et al. (ISSCC, 2017)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. - Soo-Min Lee; Kihwan Seong; Joohee Shin; Hyoungjoong Kim; Jaehyun Jeong; Shinyoung Yi 002; Juyoung Kim; Eunsu Kim; Sukhyun Jung; Sangyun Hwang; Jihun Oh; Kwanyeob Chae; et al. (ISSCC, 2020)

A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. - Soo-Min Lee; Jihoon Lim; Jaehyuk Jang; Hyoungjoong Kim; Kyunghwan Min; Woongki Min; Hyeonji Han; Gyusik Kim; Jaeyoung Kim; Chulho Kim; Sejun Jeon; Jinhoon Park; et al. (ESSCIRC, 2022)

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sang-Ho Kim; Jongwoo Lee; Joonsuk Kim (ISSCC, 2023)

A 0.036mm2 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET. - Woongki Min; Soo-Min Lee; Taejin Jang; Yunsik Jo; Hyoungjoong Kim; Younggyun Oh; Myeong-Cheol Kim; Hyeonji Han; Cheolhwan Lim; Seungjun Lee; Jihoon Lee; Yon Jun Shin; et al. (A-SSCC, 2024)

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. - Kyunghwan Min; Jahoon Jin; Soo-Min Lee; Sodam Ju; Jisu Yook; Jihoon Lee; Yunji Hong; Sungsik Park; Sang-Ho Kim; Jongwoo Lee; Hyungjong Ko (VLSI Technology and Circuits, 2024)

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Jisu Yook; Jihoon Lee; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)