2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2014)

A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design. - Sooeun Lee; Gunbok Lee; Jae-Yoon Sim; Hong-June Park; Wee Sang Park; Byungsub Kim (ICCAD, 2015)

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2016)

Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation. - JaeHyun Seo; Sangheon Lee; Kwangmin Kim; Sooeun Lee; Hyunsang Hwang; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jaehyun Ko 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2018)

An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching. - Minsoo Choi 002; Sooeun Lee; Myungguk Lee; Ji-Hoon Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2018)

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jahyun Koo 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. - Jaeyoung Seo; Jaehyun Ko 001; Kyunghyun Lim; Sooeun Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces. - Sooeun Lee; Jaeyoung Seo; Changyoon Han; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec. - Jaehyun Ko 001; Iksu Jang; Chanho Kim; Jihoon Park; Changjae Moon; Sooeun Lee; Byungsub Kim (ESSCIRC, 2022)

A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces. - Jaeyoung Seo; Sooeun Lee; Myungguk Lee; Changjae Moon; Byungsub Kim (ISSCC, 2022)

A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links. - Jaeyoung Seo; Sooeun Lee; Myungguk Lee; Changjae Moon; Byungsub Kim (IEEE J. Solid State Circuits, 2023)