Functional test pattern generation for CMOS operational amplifier. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1997)

A DFT for semi-DC fault diagnosis for switched-capacitor circuits. - Sheng-Jer Kuo; Chung Len Lee 001; Soon-Jyh Chang; Jwu E. Chen (ETW, 1999)

Structural Fault Based Specification Reduction for Testing Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Electron. Test., 2002)

A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. - Kuen-Jong Lee; Soon-Jyh Chang; Ruei-Shiuan Tzeng (Asian Test Symposium, 2003)

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 2003)

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. - Chih-Haur Huang; Kuen-Jong Lee; Soon-Jyh Chang (Asian Test Symposium, 2004)

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (Asian Test Symposium, 2004)

An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. - Heng-Yao Lin; Hui-Hsien Tsai; Bin-Da Liu; Jar-Ferr Yang; Soon-Jyh Chang (APCCAS, 2006)

Histogram Based Testing Strategy for ADC. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (ATS, 2006)

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. - Jin-Fu Lin; Soon-Jyh Chang (ISCAS, 2006)

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. - Yen-Ting Liu; Lih-Yih Chiou; Soon-Jyh Chang (ISCAS, 2006)

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. - Ying-Zu Lin; Yen-Ting Liu; Soon-Jyh Chang (CICC, 2007)

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. - Hsin-Wen Ting; Cheng-Wu Lin; Bin-Da Liu; Soon-Jyh Chang (J. Electron. Test., 2007)

A Reduced Code Linearity Test Method for Pipelined A/D Converters. - Jin-Fu Lin; Te-Chieh Kung; Soon-Jyh Chang (ATS, 2008)

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. - Hsin-Hung Ou; Soon-Jyh Chang; Bin-Da Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. - Hsin-Hung Ou; Bin-Da Liu; Soon-Jyh Chang (IEICE Trans. Electron., 2008)

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. - Chia-Ling Wei; Lu-Yao Wu; Hsiu-Hui Yang; Chien-Hung Tsai; Bin-Da Liu; Soon-Jyh Chang (IEICE Trans. Electron., 2008)

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. - Soon-Jyh Chang; Ying-Zu Lin; Yen-Ting Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Histogram-Based Testing Method for Estimating A/D Converter Performance. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (IEEE Trans. Instrum. Meas., 2008)

A Jitter Characterizing BIST with Pulse-Amplifying Technique. - An-Sheng Chao; Soon-Jyh Chang (Asian Test Symposium, 2009)

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chih-Hao Huang (Asian Test Symposium, 2009)

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. - Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu; Chun-Cheng Liu; Guan-Ying Huang (ISSCC, 2009)

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. - Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu (IEICE Trans. Electron., 2009)

Performance-driven analog placement considering boundary constraint. - Cheng-Wu Lin; Jai-Ming Lin; Chun-Po Huang; Soon-Jyh Chang (DAC, 2010)

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. - Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; Chung-Ming Huang; Chih-Hao Huang; Linkai Bu; Chih-Chung Tsai (ISSCC, 2010)

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. - Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin (IEEE J. Solid State Circuits, 2010)

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chun-Cheng Liu; Chih-Hao Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. - Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu; Chun-Cheng Liu; Guan-Ying Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. - Ying-Zu Lin; Cheng-Wu Lin; Soon-Jyh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. - Ying-Zu Lin; Soon-Jyh Chang; Ya-Ting Shyu; Guan-Ying Huang; Chun-Cheng Liu (A-SSCC, 2011)

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. - Cheng-Wu Lin; Jai-Ming Lin; Yen-Chih Chiu; Chun-Po Huang; Soon-Jyh Chang (DAC, 2011)

A SAR ADC BIST for simplified linearity test. - An-Sheng Chao; Soon-Jyh Chang; Hsin-Wen Ting (SoCC, 2011)

A Design of Linearity Built-in Self-Test for Current-Steering DAC. - Hsin-Wen Ting; Soon-Jyh Chang; Su-Ling Huang (J. Electron. Test., 2011)

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages. - Jin-Fu Lin; Soon-Jyh Chang (IEICE Trans. Electron., 2011)

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. - Jin-Fu Lin; Soon-Jyh Chang; Te-Chieh Kung; Hsin-Wen Ting; Chih-Hao Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 1-V CDS bandgap reference without on-chip resistors. - Peng-Yu Chen; Soon-Jyh Chang; Chung-Ming Huang; Jin-Fu Lin (APCCAS, 2012)

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology. - Sheng-Hsiung Lin; Jin-Fu Lin; Guan-Ying Huang; Soon-Jyh Chang (APCCAS, 2012)

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. - Cheng-Wu Lin; Chung-Lin Lee; Jai-Ming Lin; Soon-Jyh Chang (ICCAD, 2012)

A power-efficient sizing methodology of SAR ADCs. - Chun-Po Huang; Soon-Jyh Chang; Guan-Ying Huang; Cheng-Wu Lin (ISCAS, 2012)

Routability-driven placement algorithm for analog integrated circuits. - Cheng-Wu Lin; Cheng-Chung Lu; Jai-Ming Lin; Soon-Jyh Chang (ISPD, 2012)

A 1-V, 44.6 ppm/°C bandgap reference with CDS technique. - Peng-Yu Chen; Soon-Jyh Chang; Chung-Ming Huang; Chin-Fu Lin (VLSI-DAT, 2012)

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing. - I-Jen Chao; Chung-Lun Hsu; Bin-Da Liu; Soon-Jyh Chang; Chun-Yueh Huang; Hsin-Wen Ting (IEICE Trans. Electron., 2012)

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. - Ya-Ting Shyu; Ying-Zu Lin; Rong-Sing Chu; Guan-Ying Huang; Soon-Jyh Chang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers. - Ren-Li Chen; Hsin-Wen Ting; Soon-Jyh Chang (IET Circuits Devices Syst., 2012)

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. - Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin (IEEE J. Solid State Circuits, 2012)

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. - Cheng-Wu Lin; Jai-Ming Lin; Yen-Chih Chiu; Chun-Po Huang; Soon-Jyh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications. - Ren-Li Chen; Soon-Jyh Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique. - I-Jen Chao; Chia-Ming Kuo; Bin-Da Liu; Chun-Yueh Huang; Soon-Jyh Chang (ISCAS, 2013)

A successive approximation ADC with resistor-capacitor hybrid structure. - Ting-Zi Chen; Soon-Jyh Chang; Guan-Ying Huang (VLSI-DAT, 2013)

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. - Ying-Zu Lin; Chun-Cheng Liu; Guan-Ying Huang; Ya-Ting Shyu; Yen-Ting Liu; Soon-Jyh Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. - Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. - Ya-Ting Shyu; Jai-Ming Lin; Chun-Po Huang; Cheng-Wu Lin; Ying-Zu Lin; Soon-Jyh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 10b 100kS/s SAR ADC with charge recycling switching method. - Kai-Hsiang Chiang; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin (A-SSCC, 2014)

Heart rate detection through bone-conduction headset. - Tzung-Min Tsai; Hsing-Chen Lin; Shuenn-Yuh Lee; Soon-Jyh Chang (BioCAS, 2014)

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. - Cheng-Hsun Ho; Soon-Jyh Chang; Guan-Ying Huang; Che-Hsun Kuo (ISCAS, 2014)

An area- and power-efficient half-rate clock and data recovery circuit. - Yen-Long Lee; Soon-Jyh Chang; Rong-Sing Chu; Yen-Chi Chen; Jih Ren Goh; Chung-Ming Huang (ISCAS, 2014)

Low power pipelined SAR ADC with loading-free architecture. - Jia-Jhang Wu; Soon-Jyh Chang; Sheng-Hsiung Lin; Chun-Po Huang; Guan-Ying Huang (VLSI-DAT, 2014)

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder. - I-Jen Chao; Ching-Wen Hou; Bin-Da Liu; Soon-Jyh Chang; Chun-Yueh Huang (IEICE Trans. Electron., 2014)

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs. - An-Sheng Chao; Cheng-Wu Lin; Hsin-Wen Ting; Soon-Jyh Chang (IEICE Trans. Electron., 2014)

A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system. - Shuenn-Yuh Lee; Tzung-Min Tsai; Wei-Chih Lai; Soon-Jyh Chang; Stony Tai (ISCAS, 2015)

A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems. - Wei-Hao Tsai; Che-Hsun Kuo; Soon-Jyh Chang; Li-Tse Lo; Ying-Cheng Wu; Chun-Jen Chen (ISCAS, 2015)

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. - Jih Ren Goh; Yen-Long Lee; Soon-Jyh Chang (VLSI-DAT, 2015)

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. - Tien-Feng Hsu; Chun-Po Huang; I-Jen Chao; Soon-Jyh Chang (VLSI-DAT, 2015)

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS. - An-Sheng Chao; Cheng-Wu Lin; Hsin-Wen Ting; Soon-Jyh Chang (Int. J. Circuit Theory Appl., 2015)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. - Liang-Ying Lu; Ching-Yao Chang; Zhao-Hong Chen; Bo-Ting Yeh; Tai-Hua Lu; Peng-Yu Chen; Pin-Hao Tang; Kuen-Jong Lee; Lih-Yih Chiou; Soon-Jyh Chang; Chien-Hung Tsai; Chung-Ho Chen; et al. (ASP-DAC, 2016)

A pipeline ADC with latched-based ring amplifiers. - Wen-Tze Chen; Ya-Ting Shyu; Chun-Po Huang; Soon-Jyh Chang (ISCAS, 2016)

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. - Ya-Ting Shyu; Jai-Ming Lin; Che-Chun Lin; Chun-Po Huang; Soon-Jyh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs. - Chun-Po Huang; Hsin-Wen Ting; Soon-Jyh Chang (IEEE Trans. Instrum. Meas., 2016)

A Systematic Design Methodology of Asynchronous SAR ADCs. - Chun-Po Huang; Jai-Ming Lin; Ya-Ting Shyu; Soon-Jyh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 12-bit 40-MS/s calibration-free SAR ADC. - Chung-Wei Hsu; Li-Jen Chang; Chun-Po Huang; Soon-Jyh Chang (ISCAS, 2017)

A low power duobinary voltage mode transmitter. - Ming-Hung Chien; Yen-Long Lee; Jih Ren Goh; Soon-Jyh Chang (ISLPED, 2017)

A quick jitter tolerance estimation technique for bang-bang CDRs. - Yen-Long Lee; Soon-Jyh Chang (ITC-Asia, 2017)

An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator. - Chih-Huei Hou; Soon-Jyh Chang; Hao-Sheng Wu; Huan-Jui Hu; En-Ze Cun (VLSI-DAT, 2017)

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits. - Yen-Long Lee; Soon-Jyh Chang; Yen-Chi Chen; Yu-Po Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. - I-Jen Chao; Bin-Da Liu; Soon-Jyh Chang; Chun-Yueh Huang; Hsin-Wen Ting (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. - Chih-Yuan Kung; Chun-Po Huang; Chia-Chuan Li; Soon-Jyh Chang (ISCAS, 2018)

A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process. - Wen-Chia Luo; Soon-Jyh Chang; Chun-Po Huang; Hao-Sheng Wu (VLSI-DAT, 2018)

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. - Yen-Long Lee; Yu-Po Cheng; Soon-Jyh Chang; Hsin-Wen Ting (IEEE Des. Test, 2018)

A 12-b 40-MS/s Calibration-Free SAR ADC. - Chung-Wei Hsu; Soon-Jyh Chang; Chun-Po Huang; Li-Jen Chang; Ya-Ting Shyu; Chih-Huei Hou; Hwa-An Tseng; Chih-Yuan Kung; Huan-Jui Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration. - Yi-Shen Cheng; Huan-Jui Hu; Soon-Jyh Chang (ISCAS, 2019)

A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC. - Huan-Jui Hu; Yi-Shen Cheng; Soon-Jyh Chang (ISCAS, 2019)

Modified BER Test for SAR ADCs. - Chia-Chuan Li; Soon-Jyh Chang (ITC-Asia, 2020)

Resistor-Based Temperature Sensing Chip with Digital Output. - Kai-Min Chang; Yen-Ju Lin; Chia-Liang Wei; Soon-Jyh Chang (VLSI-DAT, 2020)

A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator. - Yu-Sian Lin; Soon-Jyh Chang; Chia-Ling Wei (VLSI-DAT, 2020)

Detection System for Capacitive Plantar Pressure Monitoring. - Tzung-Min Tsai; Shuenn-Yuh Lee; Soon-Jyh Chang (IEEE Access, 2020)

A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration. - Che-Wei Hsu; Soon-Jyh Chang (ISCAS, 2021)

A 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks. - Jun-Hui Fu; Soon-Jyh Chang (ISCAS, 2022)

A Physically Unclonable Function Embedded in a SAR ADC. - Yi-Ying Chen; Soon-Jyh Chang (ITC-Asia, 2022)

A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration. - Yi-Hu Wang; Soon-Jyh Chang (ISSCC, 2023)

Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. - Lih-Yih Chiou; Hong-Ming Shih; Shun-Hsiu Hsu; Zu-Cheng Sheng; Soon-Jyh Chang (ISCAS, 2024)

9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator. - Kai-Cheng Cheng; Soon-Jyh Chang; Chung-Chieh Chen; Shuo-Hong Hung (ISSCC, 2024)