A slew-rate controlled output driver using PLL as compensation circuit. - Soon-Kyun Shin; Seok-Min Jung; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (IEEE J. Solid State Circuits, 2003)

A high current driving charge pump with current regulation method. - Soon-Kyun Shin; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature. - Soon-Kyun Shin; Wang Yu; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations. - Soon-Kyun Shin; Wang Yu; Young-Hyun Jun; Jae-Whui Kim; Bai-Sun Kong; Chil-Gee Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (CICC, 2012)

A Fully Integrated, Regulatorless CMOS Power Amplifier for Long-Range Wireless Sensor Communication. - Venumadhav Bhagavatula; William Wesson; Soon-Kyun Shin; Jacques Christophe Rudell (IEEE J. Solid State Circuits, 2013)

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. - Dong-Young Chang; Carlos E. Muñoz; Denis C. Daly; Soon-Kyun Shin; Kevin Guay; Thomas Thurston; Hae-Seung Lee; Kush Gulati; Matthew Z. Straayer (ISSCC, 2014)

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (IEEE J. Solid State Circuits, 2014)