A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. - Ki-Tae Park; Doo-Gon Kim; Soonwook Hwang; Myounggon Kang; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Soon-Moon Jung; Yeong-Taek Lee; Changhyun Kim; et al. (ISSCC, 2008)

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. - Kyomin Sohn; Young-Ho Suh; Young-Jae Son; Daesik Yim; Kang-Young Kim; Dae-Gi Bae; Ted Kang; Hoon Lim; Soon-Moon Jung; Hyun-Geun Byun; Young-Hyun Jun; Kinam Kim (ISSCC, 2008)

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. - Ki-Tae Park; Myounggon Kang; Soonwook Hwang; Doo-Gon Kim; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Yeong-Taek Lee; Soon-Moon Jung; Changhyun Kim (IEEE J. Solid State Circuits, 2009)

24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Woojin Rim; Hoonki Kim; Keun Hwi Cho; Taeyeong Kim; Taejung Lee; Geumjong Bae; Dong-Won Kim; S. D. Kwon; Sanghoon Baek; Jonghoon Jung; Jongwook Kye; et al. (ISSCC, 2021)