Power-aware partitioned cache architectures. - Soontae Kim; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Anand Sivasubramaniam; Mary Jane Irwin; E. Geethanjali (ISLPED, 2001)

Energy Behavior of Java Applications from the Memory Perspective. - Narayanan Vijaykrishnan; Mahmut T. Kandemir; Soontae Kim; Samarjeet Singh Tomar; Anand Sivasubramaniam; Mary Jane Irwin (Java Virtual Machine Research and Technology Symposium, 2001)

Masking the Energy Behavior of DES Encryption. - Hendra Saputra; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin; Richard R. Brooks; Soontae Kim; Wei Zhang 002 (DATE, 2003)

On load latency in low-power caches. - Soontae Kim; Narayanan Vijaykrishnan; Mary Jane Irwin; Lizy Kurian John (ISLPED, 2003)

Partitioned instruction cache architecture for energy efficiency. - Soontae Kim; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Anand Sivasubramaniam; Mary Jane Irwin (ACM Trans. Embed. Comput. Syst., 2003)

Scheduling Reusable Instructions for Power Reduction. - Jie S. Hu; Narayanan Vijaykrishnan; Soontae Kim; Mahmut T. Kandemir; Mary Jane Irwin (DATE, 2004)

Optimizing Leakage Energy Consumption in Cache Bitlines. - Soontae Kim; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin (Des. Autom. Embed. Syst., 2004)

Instruction Scheduling for Low Power. - Amisha Parikh; Soontae Kim; Mahmut T. Kandemir; Narayanan Vijaykrishnan; Mary Jane Irwin (J. VLSI Signal Process., 2004)

Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. - J. Juran; Ali R. Hurson; Narayanan Vijaykrishnan; Soontae Kim (Wirel. Networks, 2004)

Area-efficient error protection for caches. - Soontae Kim (DATE, 2006)

Improving the reliability of on-chip L2 cache using redundancy. - Koustav Bhattacharya; Soontae Kim; Nagarajan Ranganathan (ICCD, 2007)

Reducing ALU and Register File Energy by Dynamic Zero Detection. - Soontae Kim (IPCCC, 2007)

Reducing non-deterministic loads in low-power caches via early cache set resolution. - Soontae Kim; Narayanan Vijaykrishnan; Mary Jane Irwin (Microprocess. Microsystems, 2007)

An energy-delay efficient 2-level data cache architecture for embedded system. - Jongmin Lee 002; Soontae Kim (ISLPED, 2009)

TEPS: Transient Error Protection Utilizing Sub-word Parallelism. - Seokin Hong; Soontae Kim (ISVLSI, 2009)

Reducing Area Overhead for Error-Protecting Large L2/L3 Caches. - Soontae Kim (IEEE Trans. Computers, 2009)

A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. - Koustav Bhattacharya; Nagarajan Ranganathan; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

SimTag: Exploiting tag bits similarity to improve the reliability of the data caches. - Jesung Kim; Soontae Kim; Yebin Lee (DATE, 2010)

Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. - Soontae Kim; Jongmin Lee 002 (ACM Great Lakes Symposium on VLSI, 2010)

Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU. - Seokin Hong; Soontae Kim (ICCD, 2010)

Fine-Grained Fault Tolerance for Process Variation-Aware Caches. - Tayyeb Mahmood; Soontae Kim (ISVLSI, 2010)

Modeling and Evaluation of Control Flow Vulnerability in the Embedded System. - Mohammad Abdur Rouf; Soontae Kim (MASCOTS, 2010)

ADSR: Angle-Based Multi-hop Routing Strategy for Mobile Wireless Sensor Networks. - Kwangcheol Shin; Kyungjun Kim; Soontae Kim (APSCC, 2011)

Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers. - Tayyeb Mahmood; Soontae Kim (CASES, 2011)

Dynamic scheduling algorithm and its schedulability analysis for certifiable dual-criticality systems. - Taeju Park; Soontae Kim (EMSOFT, 2011)

DRAM energy reduction by prefetching-based memory traffic clustering. - Yebin Lee; Soontae Kim (ACM Great Lakes Symposium on VLSI, 2011)

TLB index-based tagging for cache energy reduction. - Jongmin Lee 002; Seokin Hong; Soontae Kim (ISLPED, 2011)

Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. - Soontae Kim; Jongmin Lee 002; Jesung Kim; Seokin Hong (MICRO, 2011)

Enhanced buffer management policy that utilises message properties for delay-tolerant networks. - Kwangcheol Shin; Soontae Kim (IET Commun., 2011)

Low-cost control flow error protection by exploiting available redundancies in the pipeline. - Mohammad Abdur Rouf; Soontae Kim (ASP-DAC, 2012)

ECC string: Flexible ECC management for low-cost error protection of L2 caches. - Jeongkyu Hong; Soontae Kim (ICCD, 2012)

DRAM power-aware rank scheduling. - Sukki Kim; Soontae Kim; Yebin Lee (ISLPED, 2012)

Adopting TLB index-based tagging to data caches for tag energy reduction. - Jongmin Lee 002; Soontae Kim (ISLPED, 2012)

Traffic management strategy for delay-tolerant networks. - Kwangcheol Shin; Kyungjun Kim; Soontae Kim (J. Netw. Comput. Appl., 2012)

Resuscitating privacy-preserving mobile payment with customer in complete control. - Divyan Munirathnam Konidala; Made Harta Dwijaksara; Kwangjo Kim; Dongman Lee; Byoungcheon Lee; Daeyoung Kim 001; Soontae Kim (Pers. Ubiquitous Comput., 2012)

Predictive routing for mobile sinks in wireless sensor networks: a milestone-based approach. - Kwangcheol Shin; Soontae Kim (J. Supercomput., 2012)

AVICA: an access-time variation insensitive L1 cache architecture. - Seokin Hong; Soontae Kim (DATE, 2013)

Skinflint DRAM system: Minimizing DRAM chip writes for low power. - Yebin Lee; Soontae Kim; Seokin Hong; Jongmin Lee 002 (HPCA, 2013)

Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling. - Tayyeb Mahmood; Soontae Kim; Seokin Hong (HPCA, 2013)

Performance-controllable shared cache architecture for multi-core soft real-time systems. - Myoungjun Lee; Soontae Kim (ICCD, 2013)

Fault buffers - Enabling near-true voltage scaling in variation-sensitive L1 caches. - Tayyeb Mahmood; Soontae Kim (Des. Autom. Embed. Syst., 2013)

Ternary cache: Three-valued MLC STT-RAM caches. - Seokin Hong; Jongmin Lee 002; Soontae Kim (ICCD, 2014)

Efficient memory reclaiming for mitigating sluggish response in mobile devices. - Minho Ju; Hyeonggyu Kim; Mincheol Kang; Soontae Kim (ICCE-Berlin, 2015)

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction. - Jongmin Lee 002; Soontae Kim (IEEE Trans. Computers, 2015)

A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU. - Seokin Hong; Soontae Kim (IEEE Trans. Computers, 2015)

Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho. - Tayyeb Mahmood; Seokin Hong; Soontae Kim (IEEE Trans. Computers, 2015)

Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories. - Jeongkyu Hong; Jesung Kim; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline. - Mohammad Abdur Rouf; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Network delay-aware energy management for mobile systems. - Minho Ju; Hyeonggyu Kim; Soontae Kim (DATE, 2016)

MofySim: A mobile full-system simulation framework for energy consumption and performance analysis. - Minho Ju; Hyeonggyu Kim; Soontae Kim (ISPASS, 2016)

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches. - Hamed Farbeh; Hyeonggyu Kim; Seyed Ghassem Miremadi; Soontae Kim (IEEE Trans. Computers, 2016)

Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures. - Seokin Hong; Soontae Kim (IEEE Trans. Computers, 2016)

RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving. - Yebin Lee; Soontae Kim (IEEE Trans. Computers, 2016)

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems. - Jongmin Lee 002; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches. - Jeongkyu Hong; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System. - Yebin Lee; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Partial Row Activation for Low-Power DRAM System. - Yebin Lee; Hyeonggyu Kim; Seokin Hong; Soontae Kim (HPCA, 2017)

Smart ECC Allocation Cache Utilizing Cache Data Space. - Jeongkyu Hong; Soontae Kim (IEEE Trans. Computers, 2017)

TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption. - Jesung Kim; Jongmin Lee 002; Soontae Kim (IEEE Trans. Computers, 2017)

Write-Amount-Aware Management Policies for STT-RAM Caches. - Hyeonggyu Kim; Soontae Kim; Jooheung Lee (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption. - Jungwoo Park; Jongmin Lee 002; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

EAR: ECC-aided refresh reduction through 2-D zero compression. - Jeongkyu Hong; Hyeonggyu Kim; Soontae Kim (PACT, 2018)

Subpage-Aware Solid State Drive for Improving Lifetime and Performance. - Mincheol Kang; Wonyoung Lee 001; Soontae Kim (IEEE Trans. Computers, 2018)

OnNetwork+: Network Delay-Aware Management for Mobile Systems. - Hyeonggyu Kim; Minho Ju; Soontae Kim (ACM Trans. Embed. Comput. Syst., 2018)

MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. - Jungwoo Park; Myoungjun Lee; Soontae Kim; Minho Ju; Jeongkyu Hong (ACM Trans. Archit. Code Optim., 2019)

Time-sensitivity-aware shared cache architecture for multi-core embedded systems. - Myoungjun Lee; Soontae Kim (J. Supercomput., 2019)

Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages. - Wonyoung Lee 001; Mincheol Kang; Seokin Hong; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Restore-Free Mode for MLC STT-RAM Caches. - Muhammad Avais Qureshi; Hyeonggyu Kim; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Leveraging intra-page update diversity for mitigating write amplification in SSDs. - Imran Fareed; Mincheol Kang; Wonyoung Lee 001; Soontae Kim (ICS, 2020)

Freezing: Eliminating Unnecessary Drawing Computation for Low Power. - Bohun Seo; Hyeonggyu Kim; Soontae Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. - Muhammad Avais Qureshi; Jungwoo Park; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories. - Hamed Farbeh; Leila Delshadtehrani; Hyeonggyu Kim; Soontae Kim (IEEE Trans. Computers, 2021)

CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems. - Jinkwon Kim; Seokin Hong; Jeongkyu Hong; Soontae Kim (IEEE Trans. Computers, 2021)

Update Frequency-Directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads. - Imran Fareed; Mincheol Kang; Wonyoung Lee 001; Soontae Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks. - Myeongjae Jang; Jinkwon Kim; Jesung Kim; Soontae Kim (DATE, 2022)

Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance. - Junoh Moon; Mincheol Kang; Wonyoung Lee 001; Soontae Kim (DATE, 2022)

Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data. - Jinkwon Kim; Mincheol Kang; Jeongkyu Hong; Soontae Kim (HPCA, 2022)

Efficient Integrity-Tree Structure for Convolutional Neural Networks through Frequent Counter Overflow Prevention in Secure Memories. - Jesung Kim; Wonyoung Lee 001; Jeongkyu Hong; Soontae Kim (Sensors, 2022)

Estimated State-Based Optimal Path Planning and Control System for Lane-Keeping of Semi-Trailer Trucks. - Sangwon Han; Geonyeong Park; Yoonyong Ahn; Gunhee Cho; Soontae Kim; Kunsoo Huh (ITSC, 2023)

HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator. - Jinkwon Kim; Myeongjae Jang; Haejin Nam; Soontae Kim (MICRO, 2023)

Effective Emoticon Suggestion Technique Based on Active Emotional Input Using Facial Expressions and Heart Rate Signals. - Jesung Kim; Mincheol Kang; Bohun Seo; Jeongkyu Hong; Soontae Kim (Sensors, 2023)

PR-SSD: Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism. - Mincheol Kang; Wonyoung Lee 001; Jinkwon Kim; Soontae Kim (IEEE Trans. Computers, 2023)

Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks. - Myeongjae Jang; Jinkwon Kim; Haejin Nam; Soontae Kim (IEEE Trans. Computers, 2024)

Highly VM-Scalable SSD in Cloud Storage Systems. - Wonyoung Lee 001; Mincheol Kang; Soontae Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

C2C: A Framework for Critical Token Classification in Transformer-Based Inference Systems. - Myeongjae Jang; Jesung Kim; Haejin Nam; Sihyun Kim; Soontae Kim (DATE, 2025)

A Path Tracking Controller for Heavy-Duty Buses Based on Robust Model Predictive Control With a Novel Enhanced Kinematic Model. - Sangwon Han; Yuho Song; Soontae Kim; Kunsoo Huh (IEEE Trans. Intell. Veh., 2025)

Enhancing Rule-Based Hands-Off Detection With Deep Learning and Permutation Feature Analysis. - Soontae Kim; Kunsoo Huh (IEEE Trans. Intell. Veh., 2025)