PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. - Shihui Yin; Bo Zhang 105; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Mingoo Seok; Jae-sun Seo (VLSI Circuits, 2021)

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. - Bo Zhang 105; Jyotishman Saikia; Jian Meng; Dewei Wang; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-sun Seo; Mingoo Seok (CICC, 2022)

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. - Bo Zhang 105; Shihui Yin; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2023)

MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. - Bo Zhang 105; Jyotishman Saikia; Jian Meng; Dewei Wang; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

37.3 Monolithic in-Memory Computing Microprocessor for End-to-End DNN Inferencing in MRAM-Embedded 28nm CMOS Technology with 1.1Mb Weight Storage. - Soonwan Kwon; Sungmeen Myung; Jangho An; Hyunsoo Kim; Minjae Kim; Hyungwoo Lee; Wooseok Yi; Seungchul Jung; Daekun Yoon; Shinhee Han; Saeyoon Chung; Kilho Lee; et al. (ISSCC, 2025)