Arithmetic Data Path Optimization Using Borrow-Save Representation. - Sophie Belloeil; Roselyne Chotin-Avot; Habib Mehrez (ISVLSI, 2008)

Optimisation des chemins de données arithmétiques par l'utilisation des systèmes de numération redondants. (Optimization of arithmetical data paths using redundant number systems). - Sophie Belloeil (2009)

Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (ISQED, 2011)

A reference low-complexity structured ASIC. - Ludovic Noury; Sophie Dupuis; Nicolas Fel (ISCAS, 2012)

Secure JTAG Implementation Using Schnorr Protocol. - Amitabh Das; Jean DaRolt; Santosh Ghosh; Stefaan Seys; Sophie Dupuis; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (J. Electron. Test., 2013)

Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (Integr., 2013)

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. - Sophie Dupuis; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (Inf. Secur. J. A Glob. Perspect., 2013)

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. - Sophie Dupuis; Papa-Sidi Ba; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2014)

A regular fabric design methodology for applications requiring specific layout-level design rules. - Sophie Dupuis; Ludovic Noury; Nicolas Fel (Microelectron. J., 2014)

New testing procedure for finding insertion sites of stealthy hardware trojans. - Sophie Dupuis; Papa-Sidi Ba; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (DATE, 2015)

On the limitations of logic testing for detecting Hardware Trojans Horses. - Marie-Lise Flottes; Sophie Dupuis; Papa-Sidi Ba; Bruno Rouzeyre (DTIS, 2015)

Hardware Trojan prevention using layout-level design approach. - Papa-Sidi Ba; Palanichamy Manikandan; Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ECCTD, 2015)

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. - Papa-Sidi Ba; Sophie Dupuis; Palanichamy Manikandan; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ISVLSI, 2016)

Using outliers to detect stealthy hardware trojan triggering? - Papa-Sidy Ba; Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IVSW, 2016)

Hacking the Control Flow error detection mechanism. - Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (IVSW, 2017)

SI ECCS: SECure context saving for IoT devices. - Emanuele Valea; Mathieu Da Silva; Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (DTIS, 2018)

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. - Honorio Martín; Luis Entrena; Sophie Dupuis; Giorgio Di Natale (IOLTS, 2018)

A New Secure Stream Cipher for Scan Chain Encryption. - Mathieu Da Silva; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Giorgio Di Natale; Bruno Rouzeyre (IVSW, 2018)

Encryption of test data: which cipher is better? - Mathieu Da Silva; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Giorgio Di Natale; Bruno Rouzeyre (PRIME, 2018)

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. - Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IEEE Des. Test, 2018)

Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. - Emanuele Valea; Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Sophie Dupuis; Bruno Rouzeyre (DTIS, 2019)

A Comprehensive Approach to a Trusted Test Infrastructure. - Marc Merandat; Vincent Reynaud; Emanuele Valea; Jérôme Quévremont; Nicolas Valette; Paolo Maistri; Régis Leveugle; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre; Giorgio Di Natale (IVSW, 2019)

SECCS: SECure Context Saving for IoT Devices. - Emanuele Valea; Mathieu Da Silva; Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (CoRR, 2019)

Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. - Sophie Dupuis; Marie-Lise Flottes (J. Electron. Test., 2019)

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. - Florence Azaïs; Serge Bernard; Mariane Comte; Bastien Deveautour; Sophie Dupuis; Hassan El Badawi; Marie-Lise Flottes; Patrick Girard 001; Vincent Kerzèrho; Laurent Latorre; François Lefèvre; Bruno Rouzeyre; et al. (IOLTS, 2020)

A Secure Scan Controller for Protecting Logic Locking. - Quang-Linh Nguyen; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (IOLTS, 2020)

High-level Intellectual Property Obfuscation via Decoy Constants. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IOLTS, 2021)

On Preventing SAT Attack with Decoy Key-Inputs. - Quang-Linh Nguyen; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (ISVLSI, 2021)

Resynthesis-based Attacks Against Logic Locking. - Felipe Almeida; Levent Aksoy; Quang-Linh Nguyen; Sophie Dupuis; Marie-Lise Flottes; Samuel Pagliarini (ISQED, 2023)

Using Approximate Circuits Against Hardware Trojans. - Honorio Martín; Sophie Dupuis; Giorgio Di Natale; Luis Entrena (IEEE Des. Test, 2023)

Hybrid Protection of Digital FIR Filters. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Power Analysis Attack Against post-SAT Logic Locking schemes. - Nassim Riadi; Florent Bruguier; Pascal Benoit; Sophie Dupuis; Marie-Lise Flottes (ETS, 2024)

Logic Locking: Exploration of a new key-gate based on tristate logic. - Sophie Dupuis; Nassim Riadi; Clémy Moroukian; Florence Azaïs; Marie-Lise Flottes (LATS, 2024)