Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (ICCD, 2020)

RIOT-POLICE: An implementation of spatial memory safety for the RIOT operating system. - Sören Tempel; Tristan Bruns (CoRR, 2020)

Mutation-based Compliance Testing for RISC-V. - Vladimir Herdt; Sören Tempel; Daniel Große; Rolf Drechsler (ASP-DAC, 2021)

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (DAC, 2021)

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (DATE, 2021)

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (FDL, 2021)

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (J. Syst. Archit., 2021)

Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2021)

Automated Detection of Spatial Memory Safety Violations for Constrained Devices. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (ASP-DAC, 2022)

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (ATVA, 2022)

3D Visualization of Symbolic Execution Traces. - Jan Zielasko; Sören Tempel; Vladimir Herdt; Rolf Drechsler (FDL, 2022)

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (IEEE Embed. Syst. Lett., 2022)

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (J. Syst. Archit., 2022)

Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2022)

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. - Sören Tempel; Tobias Brandt; Christoph Lüth; Rolf Drechsler (FDL, 2023)

Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture. - Sören Tempel; Tobias Brandt; Christoph Lüth (TFP, 2023)

Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2023)

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (IEEE Internet Things J., 2023)

BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics. - Sören Tempel; Tobias Brandt; Christoph Lüth; Rolf Drechsler (CoRR, 2024)

Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics. - Sören Tempel; Tobias Brandt; Christoph Lüth; Christian Dietrich 001; Rolf Drechsler (DATE, 2025)