Serial Binary Addition with Polynominally Bounded Weights. - Sorin Cotofana; Stamatis Vassiliadis (ICANN, 1996)

2-1 Additions and Related Arithmetic Operations with Threshold Logic. - Stamatis Vassiliadis; Sorin Cotofana; Koen Bertels (IEEE Trans. Computers, 1996)

delta-Bit serial binary addition with linear threshold networks. - Sorin Cotofana; Stamatis Vassiliadis (J. VLSI Signal Process., 1996)

On the Design Complexity of the Issue Logic of Superscalar Machines. - Sorin Cotofana; Stamatis Vassiliadis (EUROMICRO, 1998)

Periodic symmetric functions, serial addition, and multiplication with neural networks. - Sorin Cotofana; Stamatis Vassiliadis (IEEE Trans. Neural Networks, 1998)

Vector ISA Extension for Sparse Matrix-Vector Multiplication. - Stamatis Vassiliadis; Sorin Cotofana; Pyrrhos Stathis (Euro-Par, 1999)

Serial binary multiplication with feed-forward neural networks. - Sorin Cotofana; Stamatis Vassiliadis (Neurocomputing, 1999)

Hierarchical interfaces for hardware software systems. - Tudor Niculiu; Chouki Aktouf; Sorin Cotofana (ESM, 2000)

Counter Based Superscalar Instruction Issuing. - Sorin Cotofana; Ben H. H. Juurlink; Stamatis Vassiliadis (EUROMICRO, 2000)

Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). - Marian Stanca; Stamatis Vassiliadis; Sorin Cotofana; Henk Corporaal (Euro-Par, 2000)

Multimedia Enhanced General-Purpose Processors. - Stephan Wong; Sorin Cotofana; Stamatis Vassiliadis (IEEE International Conference on Multimedia and Expo (III), 2000)

General-Purpose Processor Huffman Encoding Extension. - Stephan Wong; Sorin Cotofana; Stamatis Vassiliadis (ITCC, 2000)

Signed Digit Addition and Related Operations with Threshold Logic. - Sorin Cotofana; Stamatis Vassiliadis (IEEE Trans. Computers, 2000)

Topic 15+20: Multimedia and Embedded Systems. - Stamatis Vassiliadis; Francky Catthoor; Mateo Valero; Sorin Cotofana (Euro-Par, 2001)

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. - Mihai Sima; Sorin Cotofana; Jos T. J. van Eijndhoven; Stamatis Vassiliadis; Kees A. Vissers (FCCM, 2001)

The MOLEN rho-mu-Coded Processor. - Stamatis Vassiliadis; Stephan Wong; Sorin Cotofana (FPL, 2001)

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. - Mihai Sima; Sorin Cotofana; Stamatis Vassiliadis; Jos T. J. van Eijndhoven; Kees A. Vissers (ICCD, 2001)

Coarse Reconfigurable Multimedia Unit Extension. - Stephan Wong; Sorin Cotofana; Stamatis Vassiliadis (PDP, 2001)

Hierarchical Intellignet Mixed Simulation. - Tudor Niculiu; Sorin Cotofana (ESM, 2002)

A Sum of Absolute Differences Implementation in FPGA Hardware. - Stephan Wong; Stamatis Vassiliadis; Sorin Cotofana (EUROMICRO, 2002)

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. - Mihai Sima; Sorin Cotofana; Stamatis Vassiliadis; Jos T. J. van Eijndhoven; Kees A. Vissers (FCCM, 2002)

Field-Programmable Custom Computing Machines - A Taxonomy -. - Mihai Sima; Stamatis Vassiliadis; Sorin Cotofana; Jos T. J. van Eijndhoven; Kees A. Vissers (FPL, 2002)

Alternatives in FPGA-based SAD implementations. - Stephan Wong; Bastiaan Stougie; Sorin Cotofana (FPT, 2002)

A full adder implementation using SET based linear threshold gates. - Casper Lageweg; Sorin Cotofana; Stamatis Vassiliadis (ICECS, 2002)

A low-power threshold logic family. - Marius Padure; Sorin Cotofana; Stamatis Vassiliadis; Claudius Dan; Mircea Bodea (ICECS, 2002)

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. - Mihai Sima; Sorin Cotofana; Stamatis Vassiliadis; Jos T. J. van Eijndhoven; Kees A. Vissers (Embedded Processor Design Challenges, 2002)

Microcoded Reconfigurable Embedded Processors: Current Developments. - Stephan Wong; Stamatis Vassiliadis; Sorin Cotofana (Embedded Processor Design Challenges, 2002)

On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. - Sorin Cotofana; Casper Lageweg; Stamatis Vassiliadis (IEEE Symposium on Computer Arithmetic, 2003)

Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. - Mihai Sima; Stamatis Vassiliadis; Sorin Cotofana; Jos T. J. van Eijndhoven (ASAP, 2003)

A Hierarchical Sparse Matrix Storage Format for Vector Processors. - Pyrrhos Stathis; Stamatis Vassiliadis; Sorin Cotofana (IPDPS, 2003)

Area efficient, high speed parallel counter circuits using charge recycling threshold logic. - Peter Celinski; Derek Abbott; Sorin Dan Cotofana (ISCAS (5), 2003)

Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. - Marius Padure; Sorin Cotofana; Stamatis Vassiliadis (ISCAS (5), 2003)

A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. - Peter Celinski; Sorin Cotofana; Derek Abbott (IWANN (2), 2003)

CMOS Implementation of Generalized Threshold Functions. - Marius Padure; Sorin Cotofana; Stamatis Vassiliadis (IWANN (2), 2003)

D-SAB: A Sparse Matrix Benchmark Suite. - Pyrrhos Stathis; Stamatis Vassiliadis; Sorin Cotofana (PaCT, 2003)

Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. - Casper Lageweg; Sorin Cotofana; Stamatis Vassiliadis (VLSI-SoC (Selected Papers), 2003)

Microcode Processing: Positioning and Directions. - Stamatis Vassiliadis; Stephan Wong; Sorin Cotofana (IEEE Micro, 2003)

Binary Multiplication based on Single Electron Tunneling. - Casper Lageweg; Sorin Cotofana; Stamatis Vassiliadis (ASAP, 2004)

Efficient Hardware for Antialiasing Coverage Mask Generation. - Dan Crisu; Sorin Cotofana; Stamatis Vassiliadis; Petri Liuha (Computer Graphics International, 2004)

GRAAL - A Development Framework for Embedded Graphics Accelerators. - Dan Crisu; Sorin Cotofana; Stamatis Vassiliadis; Petri Liuha (DATE, 2004)

Compositional Memory Systems for Data Intensive Applications. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Cotofana; Jos T. J. van Eijndhoven (DATE, 2004)

Analysis of analog to digital converter based on single-electron tunnelling transistors. - Chaohong Hu; Sorin Dan Cotofana; Jianfei Jiang 002 (ISCAS (3), 2004)

Low cost and latency embedded 3D graphics reciprocation. - Dan Crisu; Stamatis Vassiliadis; Sorin Cotofana; Petri Liuha (ISCAS (2), 2004)

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. - Peter Celinski; Said F. Al-Sarawi; Derek Abbott; Sorin Cotofana; Stamatis Vassiliadis (ISVLSI, 2004)

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. - Peter Celinski; Derek Abbott; Sorin Cotofana (PATMOS, 2004)

High-Level Energy Estimation for ARM-Based SOCs. - Dan Crisu; Sorin Cotofana; Stamatis Vassiliadis; Petri Liuha (SAMOS, 2004)

Single-electron tunneling transistor implementation of periodic symmetric functions. - Chaohong Hu; Sorin Dan Cotofana; Jianfei Jiang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Analog-to-digital converter based on single-electron tunneling transistors. - Chaohong Hu; Sorin Dan Cotofana; Jianfei Jiang 002; Qiyu Cai (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Pel reconstruction on FPGA-augmented TriMedia. - Mihai Sima; Sorin Dan Cotofana; Stamatis Vassiliadis; Jos T. J. van Eijndhoven; Kees A. Vissers (IEEE Trans. Very Large Scale Integr. Syst., 2004)

CONAN - A Design Exploration Framework for Reliable Nano-Electronics. - Sorin Cotofana; Alexandre Schmid; Yusuf Leblebici; Adrian M. Ionescu; Oliver Soffke; Peter Zipf; Manfred Glesner; Antonio Rubio 001 (ASAP, 2005)

High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. - Cor Meenderinck; Sorin Cotofana; Casper Lageweg (ASAP, 2005)

Compositional Memory Systems for Multimedia Communicating Tasks. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana; Jos T. J. van Eijndhoven (DATE, 2005)

Addition Related Arithmetic Operations via Controlled Transport of Charge. - Sorin Dan Cotofana; Casper Lageweg; Stamatis Vassiliadis (IEEE Trans. Computers, 2005)

IEEE-Compliant IDCT on FPGA-Augmented TriMedia. - Mihai Sima; Sorin Cotofana; Jos T. J. van Eijndhoven; Stamatis Vassiliadis; Kees A. Vissers (J. VLSI Signal Process., 2005)

Compositional, efficient caches for a chip multi-processor. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana; Jos T. J. van Eijndhoven (DATE, 2006)

Consciousness for modeling intelligence - simulating the evolution by closure to the inverse. - Tudor Niculiu; Cristian Lupu; Sorin Cotofana (ICINCO-ICSO, 2006)

Electron counting based high-radix multiplication in single electron tunneling technology. - Cor Meenderinck; Sorin Cotofana (ISCAS, 2006)

High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology. - Cor Meenderinck; Sorin Cotofana (SAMOS, 2006)

Throughput optimization via cache partitioning for embedded multiprocessors. - Anca Mariana Molnos; Sorin Dan Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (ICSAMOS, 2006)

Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors. - Anca Mariana Molnos; Sorin Dan Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (Trans. High Perform. Embed. Archit. Compil., 2007)

A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set. - Kazeem Alagbe Gbolagade; Sorin Dan Cotofana (ACSCC, 2008)

Generalized matrix method for efficient residue to decimal conversion. - Kazeem Alagbe Gbolagade; Sorin Dan Cotofana (APCCAS, 2008)

Compositional, dynamic cache management for embedded chip multiprocessors. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana (DATE, 2008)

Bitstream compression techniques for Virtex 4 FPGAs. - Radu Andrei Stefan; Sorin Dan Cotofana (FPL, 2008)

Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits. - Saleh Safiruddin; Sorin Dan Cotofana; Ferdinand Peper (NANOARCH, 2008)

GRAAL: A Framework for Low-Power 3D Graphics Accelerators. - Ben H. H. Juurlink; Iosif Antochi; Dan Crisu; Sorin Cotofana; Stamatis Vassiliadis (IEEE Computer Graphics and Applications, 2008)

A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}. - Kazeem Alagbe Gbolagade; Sorin Dan Cotofana (ICECS, 2009)

An O(n) Residue Number System to Mixed Radix Conversion Technique. - Kazeem Alagbe Gbolagade; Sorin Cotofana (ISCAS, 2009)

Adaptive Clock Scheduling for pipelined structures. - Ben Kuiper; Sorin Cotofana (NANOARCH, 2009)

Can SG-FET Replace FET in Sleep Mode Circuits? - Marius Enachescu; Sorin Cotofana; Arjan J. van Genderen; Dimitrios Tsamados; Adrian M. Ionescu (NanoNet, 2009)

Emerging non-CMOS nanoelectronic devices - What are they?. - Nor Zaidi Haron; Said Hamdioui; Sorin Cotofana (NEMS, 2009)

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors. - Anca Mariana Molnos; Sorin Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (J. Signal Process. Syst., 2009)

Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set. - Kazeem Alagbe Gbolagade; George Razvan Voicu; Sorin Dan Cotofana (ASAP, 2010)

A unified addition structure for moduli set {2n-1, 2n, 2n+1} based on a novel RNS representation. - Somayeh Timarchi; Mahmood Fazlali; Sorin Dan Cotofana (ICCD, 2010)

An improved RNS reverse converter for the {22n+1-1, 2n, 2n-1} moduli set. - Kazeem Alagbe Gbolagade; Ricardo Chaves; Leonel Sousa; Sorin Dan Cotofana (ISCAS, 2010)

Composable local memory organisation for streaming applications on embedded MPSoCs. - Jude Angelo Ambrose; Anca Mariana Molnos; Andrew Nelson 001; Sorin Cotofana; Kees Goossens; Ben H. H. Juurlink (Conf. Computing Frontiers, 2011)

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations. - Dennis Andrade; Antonio Rubio 001; Antonio Calomarde; Sorin Dan Cotofana (ISCAS, 2011)

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits. - Yao Wang 002; Sorin Cotofana; Liang Fang (NANOARCH, 2011)

Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs. - George Razvan Voicu; Marius Enachescu; Sorin Dan Cotofana (NANOARCH, 2011)

Functional unit sharing between stacked processors in 3D integrated systems. - Demid Borodin; Winston Siauw; Sorin Dan Cotofana (ICSAMOS, 2011)

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1. - Kazeem Alagbe Gbolagade; George Razvan Voicu; Sorin Dan Cotofana (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints. - Andrew Nelson 001; Anca Molnos; Ashkan Beyranvand Nejad; Davit Mirzoyan; Sorin Cotofana; Kees Goossens (WESE, 2012)

A 3D stacked high performance scalable architecture for 3D Fourier Transform. - George Razvan Voicu; Marius Enachescu; Sorin Dan Cotofana (ICCD, 2012)

Is the road towards "Zero-Energy" paved with NEMFET-based power management? - Marius Enachescu; George Razvan Voicu; Sorin Dan Cotofana (ISCAS, 2012)

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. - Yao Wang 002; Sorin Dan Cotofana; Liang Fang (NANOARCH, 2012)

A Markovian, variation-aware circuit-level aging model. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (NANOARCH, 2012)

Stigmergic search with single electron tunneling technology based memory enhanced hubs. - Saleh Safiruddin; Sorin Cotofana; Ferdinand Peper (NANOARCH, 2012)

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. - Saleh Safiruddin; Mihai Lefter; Demid Borodin; George Razvan Voicu; Sorin Dan Cotofana (NANOARCH, 2012)

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip. - Changlin Chen; Ye Lu 003; Sorin Dan Cotofana (NOCS, 2012)

Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms. - Anca Mariana Molnos; Ashkan Beyranvand Nejad; Ba Thang Nguyen; Sorin Cotofana; Kees Goossens (Map2MPSoC/SCOPES, 2012)

Context aware slope based transistor-level aging model. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (Microelectron. Reliab., 2012)

Variation tolerant on-chip degradation sensors for dynamic reliability management systems. - Yao Wang 002; Marius Enachescu; Sorin Dan Cotofana; Liang Fang (Microelectron. Reliab., 2012)

An effective New CRT based reverse converter for a novel moduli set {22n+1 - 1, 22n+1, 22n - 1}. - Edem Kwedzo Bankas; Kazeem Alagbe Gbolagade; Sorin Dan Cotofana (ASAP, 2013)

3D stacked wide-operand adders: A case study. - George Razvan Voicu; Mihai Lefter; Marius Enachescu; Sorin Dan Cotofana (ASAP, 2013)

Is TSV-based 3D integration suitable for inter-die memory repair? - Mihai Lefter; George Razvan Voicu; Mottaqiallah Taouil; Marius Enachescu; Said Hamdioui; Sorin Dan Cotofana (DATE, 2013)

An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs. - Changlin Chen; Sorin Dan Cotofana (DSD, 2013)

Lifetime reliability assessment with aging information from low-level sensors. - Yao Wang 002; Sorin Dan Cotofana; Liang Fang (ACM Great Lakes Symposium on VLSI, 2013)

Ultra low power NEMFET based logic. - Marius Enachescu; Mihai Lefter; Antonios Bazigos; Adrian M. Ionescu; Sorin Dan Cotofana (ISCAS, 2013)

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing. - George Razvan Voicu; Sorin Dan Cotofana (NANOARCH, 2013)

A low cost method to tolerate soft errors in the NoC router control plane. - Changlin Chen; Sorin Dan Cotofana (SoCC, 2013)

A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. - Nicoleta Cucu Laurenciu; Yao Wang 002; Sorin Dan Cotofana (VLSI-SoC, 2013)

A nonlinear degradation path dependent end-of-life estimation framework from noisy observations. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (Microelectron. Reliab., 2013)

An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1, 2n + 1}. - Hillary Siewobr; Kazeem Alagbe Gbolagade; Sorin Cotofana (ISIC, 2014)

Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs. - Changlin Chen; Sorin Dan Cotofana (ISVLSI, 2014)

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. - Jiaoyan Chen 002; Christian Spagnol; Satish Grandhi; Emanuel M. Popovici; Sorin Cotofana; Alexandru Amaricai (ISVLSI, 2014)

Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs. - Changlin Chen; Sorin Cotofana (NoCArc@MICRO, 2014)

Energy effective 3D stacked hybrid NEMFET-CMOS caches. - Mihai Lefter; Marius Enachescu; George Razvan Voicu; Sorin Dan Cotofana (NANOARCH, 2014)

Robust sub-powered asynchronous logic. - Jiaoyan Chen 002; Arnaud Tisserand; Emanuel M. Popovici; Sorin Cotofana (PATMOS, 2014)

Towards energy effective LDPC decoding by exploiting channel noise variability. - Thomas Marconi; Christian Spagnol; Emanuel M. Popovici; Sorin Cotofana (VLSI-SoC, 2014)

Transmission Channel Noise Aware Energy Effective LDPC Decoding. - Thomas Marconi; Christian Spagnol; Emanuel M. Popovici; Sorin Cotofana (VLSI-SoC (Selected Papers), 2014)

Efficient Method for Designing Modulo {2n ± k} Multipliers. - Héctor Pettenghi; Sorin Cotofana; Leonel Sousa (J. Circuits Syst. Comput., 2014)

Critical transistors nexus based circuit-level aging assessment and prediction. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (J. Parallel Distributed Comput., 2014)

Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. - Yao Wang 002; Sorin Dan Cotofana; Liang Fang (J. Parallel Distributed Comput., 2014)

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. - Jiaoyan Chen 002; Arnaud Tisserand; Emanuel M. Popovici; Sorin Cotofana (ASYNC, 2015)

Enabling vertical wormhole switching in 3D NoC-bus hybrid systems. - Changlin Chen; Marius Enachescu; Sorin Dan Cotofana (DATE, 2015)

Hybrid adaptive clock management for FPGA processor acceleration. - Alexandru Gheolbanoiu; Lucian Petrica; Sorin Cotofana (DATE, 2015)

Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. - Thomas Marconi; Sorin Cotofana (ACM Great Lakes Symposium on VLSI, 2015)

ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits. - Satish Grandhi; David McCarthy; Christian Spagnol; Emanuel M. Popovici; Sorin Cotofana (ICCD, 2015)

Low cost and energy, thermal noise driven, probability modulated random number generator. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (ISCAS, 2015)

A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. - Mihai Lefter; George Razvan Voicu; Sorin Dan Cotofana (ISCAS, 2015)

Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits. - Jiaoyan Chen 002; Sorin Cotofana; Satish Grandhi; Christian Spagnol; Emanuel M. Popovici (Microelectron. Reliab., 2015)

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units. - Thien Truong Nguyen-Ly; Tushar Gupta; Manuel Pezzin; Valentin Savin; David Declercq; Sorin Cotofana (DSD, 2016)

TFET NDR skewed inverter based sensing method. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Sorin Cotofana; Costin Anghel (NANOARCH, 2016)

Error Correction Code protected Data Processing Units. - Nicoleta Cucu Laurenciu; Tushar Gupta; Valentin Savin; Sorin Dan Cotofana (NANOARCH, 2016)

A supply voltage-dependent variation aware reliability evaluation model. - Bo Yang; Emanuel M. Popovici; Michael Alan Quille; Andreas Amann; Sorin Cotofana (NANOARCH, 2016)

Brownian Circuits: Designs. - Jia Lee; Ferdinand Peper; Sorin Dan Cotofana; Makoto Naruse; Motoichi Ohtsu; Tadashi Kawazoe; Yasuo Takahashi; Tetsuya Shimokawa; Laszlo B. Kish; Tohru Kubota (Int. J. Unconv. Comput., 2016)

A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. - Xu He; Yao Wang 002; Yang Guo 003; Sorin Cotofana (ACM Great Lakes Symposium on VLSI, 2017)

LDPC-Based Adaptive Multi-Error Correction for 3D Memories. - Mihai Lefter; George Razvan Voicu; Thomas Marconi; Valentin Savin; Sorin Dan Cotofana (ICCD, 2017)

Low cost multi-error correction for 3D polyhedral memories. - Mihai Lefter; Thomas Marconi; George Razvan Voicu; Sorin Dan Cotofana (NANOARCH, 2017)

Fast and accurate workload-level neural network based IC energy consumption estimation. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (SMACD, 2017)

Haar-based interconnect coding for energy effective medium/long range data transport. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (SoCC, 2017)

Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links. - Changlin Chen; Yaowen Fu; Sorin Cotofana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders. - George Razvan Voicu; Sorin Dan Cotofana (IEEE Trans. Emerg. Top. Comput., 2017)

On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps. - Yande Jiang; Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (ISCAS, 2018)

Complementary Arranged Graphene Nanoribbon-based Boolean Gates. - Yande Jiang; Nicoleta Cucu Laurenciu; Sorin Cotofana (NANOARCH, 2018)

Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. - Marius Enachescu; Mihai Lefter; George Razvan Voicu; Sorin Dan Cotofana (IEEE Trans. Emerg. Top. Comput., 2018)

A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement. - Vasileios G. Ntinas; Antonio Rubio 001; Georgios Ch. Sirakoulis; Sorin Dan Cotofana (ISCAS, 2019)

Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model. - He Wang 013; Nicoleta Cucu Laurenciu; Yande Jiang; Sorin Dan Cotofana (ISCAS, 2019)

Graphene Nanoribbon-based Synapses with Versatile Plasticity. - He Wang 013; Nicoleta Cucu Laurenciu; Yande Jiang; Sorin Dan Cotofana (NANOARCH, 2019)

On Basic Boolean Function Graphene Nanoribbon Conductance Mapping. - Yande Jiang; Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

n-bit Data Parallel Spin Wave Logic Gate. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Sorin Cotofana; Said Hamdioui (DATE, 2020)

Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA. - Mairin Kroes; Lucian Petrica; Sorin Cotofana; Michaela Blott (GECCO, 2020)

4-output Programmable Spin Wave Logic Gate. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Christoph Adelmann; Florin Ciubotaru; Said Hamdioui; Sorin Cotofana (ICCD, 2020)

Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. - Lucian Petrica; Tobias Alonso; Mairin Kroes; Nicholas J. Fraser; Sorin Cotofana; Michaela Blott (FPT, 2020)

Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. - Theodoros Panagiotis Chatzinikolaou; Iosif-Angelos Fyrigos; Rafailia-Eleni Karamani; Vasileios G. Ntinas; Giorgos Dimitrakopoulos; Sorin Cotofana; Georgios Ch. Sirakoulis (ISCAS, 2020)

Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron. - He Wang 013; Nicoleta Cucu Laurenciu; Yande Jiang; Sorin Dan Cotofana (ISCAS, 2020)

2-Output Spin Wave Programmable Logic Gate. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Christoph Adelmann; Florin Ciubotaru; Sorin Cotofana; Said Hamdioui (ISVLSI, 2020)

A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. - Jinkai Wang; Chenyu Lian; Yining Bai; Guanda Wang; Zhizhong Zhang 004; Zhenyi Zheng; Lei Chen; Kelian Lin; Kun Zhang 030; Youguang Zhang; Xiulong Wu; Sorin Cotofana; et al. (IEEE Trans. Circuits Syst., 2020)

Reliability Aware Design and Lifetime Management of Computing Platforms. - Nicoleta Cucu Laurenciu; Sorin Dan Cotofana (IEEE Trans. Emerg. Top. Comput., 2020)

Fan-out of 2 Triangle Shape Spin Wave Logic Gates. - Abdulqader Nael Mahmoud; Christoph Adelmann; Frederic Vanderveken; Sorin Cotofana; Florin Ciubotaru; Said Hamdioui (DATE, 2021)

Spin Wave Based 4-2 Compressor. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Sorin Cotofana; Said Hamdioui (ICECS, 2021)

Spin Wave Based Full Adder. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Sorin Cotofana; Said Hamdioui (ISCAS, 2021)

Achieving Wave Pipelining in Spin Wave Technology. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Christoph Adelmann; Florin Ciubotaru; Said Hamdioui; Sorin Cotofana (ISQED, 2021)

Graphene-Based Artificial Synapses with Tunable Plasticity. - He Wang 013; Nicoleta Cucu Laurenciu; Yande Jiang; Sorin Cotofana (ACM J. Emerg. Technol. Comput. Syst., 2021)

Spin Wave Normalization Toward All Magnonic Circuits. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Christoph Adelmann; Florin Ciubotaru; Sorin Cotofana; Said Hamdioui (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. - Xiaotao Jia; Jianlei Yang 001; Runze Liu 001; Xueyan Wang; Sorin Dan Cotofana; Weisheng Zhao (IEEE Trans. Neural Networks Learn. Syst., 2021)

Would Magnonic Circuits Outperform CMOS Counterparts? - Abdulqader Nael Mahmoud; Nicoleta Cucu Laurenciu; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Sorin Cotofana; Said Hamdioui (ACM Great Lakes Symposium on VLSI, 2022)

Non-Binary Spin Wave Based Circuit Design. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Said Hamdioui; Sorin Cotofana (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Spin Wave Based Approximate Computing. - Abdulqader Nael Mahmoud; Frederic Vanderveken; Florin Ciubotaru; Christoph Adelmann; Said Hamdioui; Sorin Cotofana (IEEE Trans. Emerg. Top. Comput., 2022)

Spin Wave Threshold Logic Gates. - Arne Van Zegbroeck; Pantazis Anagnostou; Said Hamdioui; Christoph Adelmann; Florin Ciubotaru; Sorin Cotofana (NANOARCH, 2023)

Roadmap for Unconventional Computing with Nanotechnology. - Giovanni Finocchio; Supriyo Bandyopadhyay; Peng Lin; Gang Pan 001; J. Joshua Yang; Riccardo Tomasello; Christos Panagopoulos; Mario Carpentieri; Vito Puliafito; Johan Åkerman; Hiroki Takesue; Amit Ranjan Trivedi; et al. (CoRR, 2023)

An Energy-Efficient Graphene-based Spiking Neural Network Architecture for Pattern Recognition. - Nicoleta Cucu Laurenciu; Charles Timmermans; Sorin Dan Cotofana (ISCAS, 2024)

Spintronic logic: from transducers to logic gates and circuits. - Christoph Adelmann; Florin Ciubotaru; Fanfan Meng; Sorin Cotofana; Sebastien Couet (CoRR, 2024)

Spin Wave Threshold Gate. - Arne Van Zegbroeck; Pantazis Anagnostou; Said Hamdioui; Christoph Adelmann; Florin Ciubotaru; Sorin Cotofana (CoRR, 2024)

CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. - Huiyi Gu; Xiaotao Jia; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Youguang Zhang; Sorin Dan Cotofana; Weisheng Zhao (IEEE Trans. Emerg. Top. Comput., 2024)

Two Cascaded Spin Wave Majority Gates Operation Under Continuous and Pulse Modes. - Abdulqader Nael Mahmoud; Florin Ciubotaru; Frederic Vanderveken; Christoph Adelmann; Sorin Cotofana; Said Hamdioui (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. - Xiaotao Jia; Huiyi Gu; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Weitao Pan; Youguang Zhang; Sorin Cotofana; Weisheng Zhao (IEEE Trans. Neural Networks Learn. Syst., 2024)

A Convoluted Journey from CMOS to Spin Waves. - Pantazis Anagnostou; Arne Van Zegbroeck; Said Hamdioui; Christoph Adelmann; Florin Ciubotaru; Sorin Cotofana (ISCAS, 2025)

Graphene-based, Frequency-Domain Self-Trigger for Low SNR Air Showers-induced Pulses. - Nicoleta Cucu Laurenciu; Charles Timmermans; Sorin Dan Cotofana (ISCAS, 2025)

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. - Fanfan Meng; Siang-Yun Lee; Odysseas Zografos; Mohit Gupta 004; Van D. Nguyen; Giovanni De Micheli; Sorin Cotofana; Inge Asselberghs; Christoph Adelmann; Gouri Sankar Kar; Sebastien Couet; Florin Ciubotaru (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)