Architectural Adaptations for Hierarchical Image Processing/Transmission. - Nikitas A. Alexandridis; Sotirios G. Ziavras; P. D. Tsanakas (ICC, 1986)

Improved algorithms for translation of pictures represented by leaf codes. - Sotirios G. Ziavras; Nikitas A. Alexandridis (Image Vis. Comput., 1988)

On the mapping problem for multi-level systems. - Sotirios G. Ziavras (SC, 1989)

Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. - Sotirios G. Ziavras (ICPP (1), 1990)

Connection Machine Results for Pyramid Embedding Algorithms. - Sotirios G. Ziavras (CONPAR, 1992)

Processor Allocation for a Class of Hypercube-Like Supercomputers. - Nagasimha G. Haravu; Sotirios G. Ziavras (SC, 1992)

On the Problem of Expanding Hypercube-Based Systems. - Sotirios G. Ziavras (J. Parallel Distributed Comput., 1992)

Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study. - Sotirios G. Ziavras; Muhammad A. Siddiqui (Concurr. Pract. Exp., 1993)

Connected component labelling on the BLITZEN massively parallel processor. - Sotirios G. Ziavras (Image Vis. Comput., 1993)

Efficient Mapping Algorithms for a Class of Hierarchical Systems. - Sotirios G. Ziavras (IEEE Trans. Parallel Distributed Syst., 1993)

Generalized reduced hypercube interconnection networks for massively parallel computers. - Sotirios G. Ziavras (Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994)

A class of scalable architectures for high-performance, cost-effective parallel computing. - Sotirios G. Ziavras (SPDP, 1994)

High-performance emulation of hierarchical structures on hypercube supercomputers. - Sotirios G. Ziavras; Devenkumar P. Shah (Concurr. Pract. Exp., 1994)

Adaptive Multiresolution Structures for Image Processing on Parallel Computers. - Sotirios G. Ziavras; Peter Meer (J. Parallel Distributed Comput., 1994)

RH: A Versatile Family of Reduced Hypercube Interconnection Networks. - Sotirios G. Ziavras (IEEE Trans. Parallel Distributed Syst., 1994)

Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. - Sotirios G. Ziavras; Michalis A. Sideras (Int. J. Pattern Recognit. Artif. Intell., 1995)

Scalable Multifolded Hypercubes for versatile Parallel Computers. - Sotirios G. Ziavras (Parallel Process. Lett., 1995)

Performance Analysis for an Important Class of Parallel-Processing Networks. - Sotirios G. Ziavras (ISPAN, 1996)

Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. - Xi Li; Sotirios G. Ziavras; Constantine N. Manikopoulos (Concurr. Pract. Exp., 1996)

Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. - Sotirios G. Ziavras; Arup Mukherjee (Parallel Comput., 1996)

Parallel generation of adaptive multiresolution structures for image processing. - Xi Li; Sotirios G. Ziavras; Constantine N. Manikopoulos (Concurr. Pract. Exp., 1997)

Robust interprocessor connections for very-high performance. - Sotirios G. Ziavras; Qian Wang (Robust Communication Networks: Interconnection and Survivability, 1998)

Network Embedding Techniques for a New Class of Feasible Parallel Architectures. - Qian Wang; Sotirios G. Ziavras (Applied Informatics, 1999)

Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. - Qian Wang; Sotirios G. Ziavras (ISPAN, 1999)

Evaluating the communications capabilities of the generalized hypercube interconnection network. - Sotirios G. Ziavras; Sanjay Krishnamurthy (Concurr. Pract. Exp., 1999)

Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing. - Sotirios G. Ziavras (VLSI Design, 1999)

Versatile Processor Design for Efficiency and High Performance. - Sotirios G. Ziavras (ISPAN, 2000)

A new-generation parallel computer and its performance evaluation. - Sotirios G. Ziavras; Haim Grebel; Anthony T. Chronopoulos; Florent Marcelli (Future Gener. Comput. Syst., 2000)

A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers. - Taras I. Golota; Sotirios G. Ziavras (VLSI Design, 2001)

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). - Segreen Ingersoll; Sotirios G. Ziavras (Microprocess. Microsystems, 2002)

Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. - Xizhen Xu; Sotirios G. Ziavras (CATA, 2003)

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. - Xiaofang Wang; Sotirios G. Ziavras (FPT, 2003)

Load Balancing on PC Clusters with the Super-Programming Model. - Dejiang Jin; Sotirios G. Ziavras (ICPP Workshops, 2003)

Parallel Direct Solution of Linear Equations on FPGA-Based Machines. - Xiaofang Wang; Sotirios G. Ziavras (IPDPS, 2003)

Viable Architectures for High-Performance Computing. - Sotirios G. Ziavras; Qian Wang; Paraskevi Papathanasiou (Comput. J., 2003)

Processor design based on dataflow concurrency. - Sotirios G. Ziavras (Microprocess. Microsystems, 2003)

A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. - Xiaofang Wang; Sotirios G. Ziavras (IPDPS, 2004)

Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. - Xiaofang Wang; Sotirios G. Ziavras (Concurr. Comput. Pract. Exp., 2004)

A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters. - Dejiang Jin; Sotirios G. Ziavras (IEICE Trans. Inf. Syst., 2004)

FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. - Satchidanand G. Haridas; Sotirios G. Ziavras (Parallel Algorithms Appl., 2004)

A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. - Dejiang Jin; Sotirios G. Ziavras (IEEE Trans. Parallel Distributed Syst., 2004)

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. - Jie S. Hu; Greg M. Link; Johnsy K. John; Shuai Wang 006; Sotirios G. Ziavras (Asia-Pacific Computer Systems Architecture Conference, 2005)

An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. - Xizhen Xu; Sotirios G. Ziavras; Tae-Gyu Chang (EUC, 2005)

FPGA-Based Vector Processing for Solving Sparse Sets of Equations. - Muhammad Z. Hasan; Sotirios G. Ziavras (FCCM, 2005)

A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. - Xiaofang Wang; Sotirios G. Ziavras (FPT, 2005)

Load-balanced CICB packet switch with support for long round-trip times. - Roberto Rojas-Cessa; Ziqian Dong; Sotirios G. Ziavras (GLOBECOM, 2005)

Optimizing the Thermal Behavior of Subarrayed Data Caches. - Johnsy K. John; Jie S. Hu; Sotirios G. Ziavras (ICCD, 2005)

H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. - Xizhen Xu; Sotirios G. Ziavras (ICCD, 2005)

A hierarchically-controlled SIMD machine for 2D DCT on FPGAs. - Xizhen Xu; Sotirios G. Ziavras (SoCC, 2005)

FPGA-based vector processor for algebraic equation solvers. - Hongyan Yang; Sotirios G. Ziavras (SoCC, 2005)

Modeling distributed data representation and its effect on parallel data accesses. - Dejiang Jin; Sotirios G. Ziavras (J. Parallel Distributed Comput., 2005)

In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. - Jie S. Hu; Shuai Wang 006; Sotirios G. Ziavras (DSN, 2006)

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. - Xiaofang Wang; Sotirios G. Ziavras (ICCD, 2006)

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ICSAMOS, 2006)

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers. - Xizhen Xu; Sotirios G. Ziavras (IEICE Trans. Inf. Syst., 2006)

Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. - Xiaofang Wang; Sotirios G. Ziavras; Jie S. Hu (ERSA, 2007)

Resource management for dynamically-challenged reconfigurable systems. - Muhammad Z. Hasan; Sotirios G. Ziavras (ETFA, 2007)

Measuring Network Parameters with Hardware Support. - Kanchan Devarakonda; Sotirios G. Ziavras; Roberto Rojas-Cessa (ICNS, 2007)

A Study of Data Exchange Protocols for the Grid Computing Environment. - Dejiang Jin; Sotirios G. Ziavras (ICNS, 2007)

Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. - Xiaofang Wang; Sotirios G. Ziavras (ISQED, 2007)

Asymmetrically Banked Value-Aware Register Files. - Shuai Wang 006; Hongyan Yang; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2007)

Vector Processing Support for FPGA-Oriented High Performance Applications. - Hongyan Yang; Shuai Wang 006; Sotirios G. Ziavras; Jie S. Hu (ISVLSI, 2007)

Runtime Partial Reconfiguration for Embedded Vector Processors. - Muhammad Z. Hasan; Sotirios G. Ziavras (ITNG, 2007)

FPGA-based Vector Processing for Matrix Operations. - Hongyan Yang; Sotirios G. Ziavras; Jie S. Hu (ITNG, 2007)

Reconfiguration support for vector operations. - Hongyan Yang; Sotirios G. Ziavras; Jie S. Hu (Int. J. High Perform. Syst. Archit., 2007)

Coprocessor design to support MPI primitives in configurable multiprocessors. - Sotirios G. Ziavras; Alexandros V. Gerbessiotis; Rohan Bafna (Integr., 2007)

Partially Reconfigurable Vector Processor for Embedded Applications. - Muhammad Z. Hasan; Sotirios G. Ziavras (J. Comput., 2007)

BTB Access Filtering: A Low Energy and High Performance Design. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2008)

Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior . - Xin Tang; Constantine N. Manikopoulos; Sotirios G. Ziavras (Int. J. Netw. Secur., 2008)

Asymmetrically banked value-aware register files for low-energy and high-performance. - Shuai Wang 006; Hongyan Yang; Jie S. Hu; Sotirios G. Ziavras (Microprocess. Microsystems, 2008)

Self-Adaptive Data Caches for Soft-Error Reliability. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Robust scalability analysis and SPM case studies. - Dejiang Jin; Sotirios G. Ziavras (J. Supercomput., 2008)

Social Inference Risk Modeling in Mobile and Social Applications. - Sara Motahari; Sotirios G. Ziavras; Mor Naaman; Mohamed Ismail; Quentin Jones (CSE (3), 2009)

Exploiting narrow-width values for thermal-aware register file designs. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras; Sung Woo Chung (DATE, 2009)

Identity Inference as a Privacy Risk in Computer-Mediated Communication. - Sara Motahari; Sotirios G. Ziavras; Richard P. Schuler; Quentin Jones (HICSS, 2009)

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. - Spiridon F. Beldianu; Roberto Rojas-Cessa; Eiji Oki; Sotirios G. Ziavras (ICCCN, 2009)

Preventing Unwanted Social Inferences with Classification Tree Analysis. - Sara Motahari; Sotirios G. Ziavras; Quentin Jones (ICTAI, 2009)

Designing for different levels of social inference risk. - Sara Motahari; Sotirios G. Ziavras; Quentin Jones (SOUPS, 2009)

Customized kernel execution on reconfigurable hardware for embedded applications. - Muhammad Z. Hasan; Sotirios G. Ziavras (Microprocess. Microsystems, 2009)

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Computers, 2009)

On the Exploitation of Narrow-Width Values for Improving Register File Reliability. - Jie S. Hu; Shuai Wang 006; Sotirios G. Ziavras (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. - Imtiaz Sajid; Sotirios G. Ziavras; Muhammad Mansoor Ahmed (DSD, 2010)

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2010)

FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization. - Imtiaz Sajid; Sotirios G. Ziavras; Muhammad Mansoor Ahmed (VISAPP (2), 2010)

Novel FPGA-Based Signature Matching for Deep Packet Inspection. - Nitesh B. Guinde; Sotirios G. Ziavras (WISTP, 2010)

Efficient hardware support for pattern matching in network intrusion detection. - Nitesh B. Guinde; Sotirios G. Ziavras (Comput. Secur., 2010)

Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. - Spiridon F. Beldianu; Roberto Rojas-Cessa; Eiji Oki; Sotirios G. Ziavras (IEEE Commun. Lett., 2010)

Online anonymity protection in computer-mediated communication. - Sara Motahari; Sotirios G. Ziavras; Quentin Jones (IEEE Trans. Inf. Forensics Secur., 2010)

On-chip Vector Coprocessor Sharing for Multicores. - Spiridon F. Beldianu; Sotirios G. Ziavras (PDP, 2011)

Message from General Chairs. - Ioannis Vlahava; Sotirios G. Ziavras (ICTAI, 2012)

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IET Comput. Digit. Tech., 2012)

Versatile design of shared vector coprocessors for multicores. - Spiridon F. Beldianu; Christopher Dahlberg; Timothy Steele; Sotirios G. Ziavras (Microprocess. Microsystems, 2012)

Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. - Imtiaz Sajid; Muhammad Mansoor Ahmed; Sotirios G. Ziavras (J. Signal Process. Syst., 2012)

FPGA and ASIC square root designs for high performance and power efficiency. - Shashank Suresh; Spiridon F. Beldianu; Sotirios G. Ziavras (ASAP, 2013)

Packet classification using rule caching. - Nitesh B. Guinde; Roberto Rojas-Cessa; Sotirios G. Ziavras (IISA, 2013)

Efficient on-chip vector processing for multicore processors. - Spiridon F. Beldianu; Sotirios G. Ziavras (ISSoC, 2013)

Multicore-based vector coprocessor sharing for performance and energy gains. - Spiridon F. Beldianu; Sotirios G. Ziavras (ACM Trans. Embed. Comput. Syst., 2013)

ASIC Design of Shared Vector Accelerators for Multicore Processors. - Spiridon F. Beldianu; Sotirios G. Ziavras (SBAC-PAD, 2014)

A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies. - Xiaofang Wang; Sotirios G. Ziavras (Int. J. Comput. Sci. Eng., 2015)

Modular vector processor architecture targeting at data-level parallelism. - Seyed A. Rooholamin; Sotirios G. Ziavras (Microprocess. Microsystems, 2015)

A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines. - Khondaker Musfakus Salehin; Roberto Rojas-Cessa; Sotirios G. Ziavras (IEEE Syst. J., 2015)

Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. - Spiridon F. Beldianu; Sotirios G. Ziavras (IEEE Trans. Computers, 2015)

Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration. - Yaojie Lu 002; Seyed Amin Rooholamin; Sotirios G. Ziavras (ISVLSI, 2016)

Wireless sensor network-based infrastructure damage detection constrained by energy consumption. - William Contreras; Sotirios G. Ziavras (UEMCON, 2016)

Wireless sensor network-based pattern matching technique for the circumvention of environmental and stimuli-related variability in structural health monitoring. - William Contreras; Sotirios G. Ziavras (IET Wirel. Sens. Syst., 2016)

Vector Coprocessor Virtualization for Simultaneous Multithreading. - Yaojie Lu 002; Seyed A. Rooholamin; Sotirios G. Ziavras (ACM Trans. Embed. Comput. Syst., 2016)

Efficient infrastructure damage detection and localization using wireless sensor networks, with cluster generation for monitoring damage progression. - William Contreras; Sotirios G. Ziavras (UEMCON, 2017)

Efficient structural health monitoring with wireless sensor networks using a vibration-based frequency domain pattern matching technique. - William Contreras; Sotirios G. Ziavras (UEMCON, 2017)

Instruction Fusion for Multiscalar and Many-Core Processors. - Yaojie Lu 002; Sotirios G. Ziavras (Int. J. Parallel Program., 2017)

Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks. - William Contreras; Sotirios G. Ziavras (IEEE Trans. Syst. Man Cybern. Syst., 2020)