Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. - Sou-Chi Chang; Ahmet Ceyhan; Vachan Kumar; Azad Naeemi (ISLPED, 2014)

Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. - Sou-Chi Chang; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young; Azad Naeemi (CoRR, 2016)

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. - Yuan-Chun Luo; Anni Lu; Yandong Luo; Sou-Chi Chang; Uygar Avci; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)