A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. - Masahito Matsuo; Hiroyuki Kondo; Yukari Takata; Souichi Kobayashi; Mitsugu Satoh; Toyohiko Yoshida; Yuichi Saito; Jun-ichi Hinata (ICCD, 1994)

System performance and energy consumption improvement methodology by delay adjustable synchronizer. - Masanori Kurimoto; Yasuhiko Takahashi; Yuji Fujiwara; Mamoru Sakugawa; Souichi Kobayashi; Hiroyuki Kondo (A-SSCC, 2011)