PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. - P. E. Allen; Soumitra Bose; Edmund M. Clarke; Spiro Michaylov (CADE, 1988)

Verifying pipelined hardware using symbolic logic simulation. - Soumitra Bose; Allan L. Fisher (ICCD, 1989)

Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. - Soumitra Bose; Prathima Agrawal (DAC, 1992)

PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. - Soumitra Bose; Edmund M. Clarke; David E. Long; Spiro Michaylov (J. Autom. Reason., 1992)

Logic systems for path delay test generation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (EURO-DAC, 1993)

Delay fault testability evaluation through timing simulation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1993)

Generation of Compact Delay Tests by Multiple-Path Activation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (ITC, 1993)

A Path Delay Fault Simulator for Sequential Circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (VLSI Design, 1993)

The optimistic update theorem for path delay testing in sequential circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (J. Electron. Test., 1993)

Path delay fault simulation of sequential circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Sequential logic path delay test generation by symbolic analysis. - Soumitra Bose; Vishwani D. Agrawal (Asian Test Symposium, 1995)

Algorithms for Switch Level Delay Fault Simulation. - Soumitra Bose; Vishwani D. Agrawal; Thomas G. Szymanski (ITC, 1997)

Deriving Logic Systems for Path Delay Test Generation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1998)

Concurrent fault simulation on message passing multicomputers. - Soumitra Bose; Prathima Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A rated-clock test method for path delay faults. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Automated Modeling of Custom Digital Circuits for Test. - Soumitra Bose (DATE, 2002)

Extraction of Schematic Array Models for Memory Circuits. - Soumitra Bose; Amit Nandi (DATE, 2004)

Modeling Custom Digital Circuits for Test. - Soumitra Bose (J. Electron. Test., 2004)

Schematic array models for associative and non-associative memory circuits. - Soumitra Bose; Amit Nandi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Fault Coverage Estimation for Non-Random Functional Input Sequences. - Soumitra Bose; Vishwani D. Agrawal (ITC, 2006)

Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. - Vishwani D. Agrawal; Soumitra Bose; Vijay Gangaram (VTS, 2006)

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. - Soumitra Bose; Vishwani D. Agrawal (ITC, 2007)

Delay fault simulation with bounded gate delay mode. - Soumitra Bose; Hillary Grimes; Vishwani D. Agrawal (ITC, 2007)

Delay Test Quality Evaluation Using Bounded Gate Delays. - Soumitra Bose; Vishwani D. Agrawal (VTS, 2007)