Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits. - Cattalen Pelard; Edward Gebara; Andrew J. Kim; Michael G. Vrazel; Franklin Bien; Youngsik Hur; Moonkyun Maeng; Soumya Chandramouli; Carl Chun; Sanjay Bajekal; Stephen E. Ralph; Bruce Schmukler; et al. (IEEE J. Solid State Circuits, 2004)

A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels. - Carl Chun; Youngsik Hur; Moonkyun Maeng; Hyoungsoo Kim; Soumya Chandramouli; Edward Gebara; Joy Laskar (ISCAS (5), 2005)

A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling. - Hyoungsoo Kim; Youngsik Hur; Moonkyun Maeng; Franklin Bien; Soumya Chandramouli; Edward Gebara; Joy Laskar (IWSOC, 2005)

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS. - Soumya Chandramouli; Franklin Bien; Hyoungsoo Kim; Edward Gebara; Joy Laskar (ESSCIRC, 2007)

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology. - Franklin Bien; Soumya Chandramouli; Hyoungsoo Kim; Edward Gebara; Joy Laskar (ISCAS, 2007)

A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication. - Hyoungsoo Kim; Franklin Bien; Youngsik Hur; Soumya Chandramouli; Jeongwon Cha; Edward Gebara; Joy Laskar (ISCAS, 2007)

A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS. - Ashkan Roshan-Zamir; Takayuki Iwai; Yang-Hang Fan; Ankur Kumar; Hae-Woong Yang; Lee Sledjeski; John Hamilton; Soumya Chandramouli; Arlo Aude; Samuel Palermo (CICC, 2018)

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS. - Ashkan Roshan-Zamir; Takayuki Iwai; Yang-Hang Fan; Ankur Kumar; Hae-Woong Yang; Lee Sledjeski; John Hamilton; Soumya Chandramouli; Arlo Aude; Samuel Palermo (IEEE J. Solid State Circuits, 2019)