Assessing carbon nanotube bundle interconnect for future FPGA architectures. - Soumya Eachempati; Arthur Nieuwoudt; Aman Gayasen; Narayanan Vijaykrishnan; Yehia Massoud (DATE, 2007)

Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. - Soumya Eachempati; Narayanan Vijaykrishnan; Arthur Nieuwoudt; Yehia Massoud (ISVLSI, 2007)

MIRA: A Multi-layered On-Chip Interconnect Router Architecture. - Dongkook Park; Soumya Eachempati; Reetuparna Das; Asit K. Mishra; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2008)

Reconfigurable BDD based quantum circuits. - Soumya Eachempati; Vinay Saripalli; Narayanan Vijaykrishnan; Suman Datta (NANOARCH, 2008)

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. - Reetuparna Das; Soumya Eachempati; Asit K. Mishra; Narayanan Vijaykrishnan; Chita R. Das (HPCA, 2009)

A case for dynamic frequency tuning in on-chip networks. - Asit K. Mishra; Reetuparna Das; Soumya Eachempati; Ravishankar R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (MICRO, 2009)

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. - Yuan Xie 001; Soumya Eachempati; Aditya Yanamandra; Vijaykrishnan Narayanan; Mary Jane Irwin (NANOARCH, 2009)

Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. - Soumya Eachempati; Narayanan Vijaykrishnan; Arthur Nieuwoudt; Yehia Massoud (IET Circuits Devices Syst., 2009)

Optimizing power and performance for reliable on-chip networks. - Aditya Yanamandra; Soumya Eachempati; Niranjan Soundararajan; Vijaykrishnan Narayanan; Mary Jane Irwin; Ramakrishnan Krishnan (ASP-DAC, 2010)

Automated mapping for reconfigurable single-electron transistor arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (DAC, 2011)

RAFT: A router architecture with frequency tuning for on-chip networks. - Asit K. Mishra; Aditya Yanamandra; Reetuparna Das; Soumya Eachempati; Ravi R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (J. Parallel Distributed Comput., 2011)

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (ACM J. Emerg. Technol. Comput. Syst., 2013)