Soumya J.

Orcid: 0000-0003-2276-1698

According to our database1, Soumya J. authored at least 47 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Improving the Functional Coverage Closure of Network-on-Chip using Particle Swarm Optimization.
Proceedings of the 19th International Conference on Synthesis, 2023

Improving Functional Coverage of Network-On-Chip Using Differential Evolution.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Improving the Functional Coverage Closure of Network-on-Chip using Genetic Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
NoC Application Mapping Optimization Using Reinforcement Learning.
ACM Trans. Design Autom. Electr. Syst., 2022

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation.
IEEE Access, 2022

Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip.
J. Syst. Archit., 2021

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA.
IEEE Access, 2021

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA.
IEEE Access, 2021

RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Angle and Height Estimation Technique for Aerial Vehicles using mmWave FMCW Radar.
Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

Object Classification Technique for mmWave FMCW Radars using Range-FFT Features.
Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

2020
Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Self-Powered Long-range Wireless IoT Device based on LoRaWAN.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.
ACM J. Emerg. Technol. Comput. Syst., 2019

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation.
J. Exp. Theor. Artif. Intell., 2019

Long-range & Self-powered IoT Devices for Agriculture & Aquaponics Based on Multi-hop Topology.
Proceedings of the 5th IEEE World Forum on Internet of Things, 2019

Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization.
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

2018
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design.
Proceedings of the TENCON 2018, 2018

Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization.
Proceedings of the TENCON 2018, 2018

Dn-FTR: Fault-tolerant routing algorithm for Mesh based network-on-chip.
Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Sensor Data Compression Based on Re-Quantization of Sensor Data.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Design of Software and Data Analytics for Self-Powered Wireless IoT Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Self-powered IoT Device based on Energy Harvesting for Remote Applications.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018

2017
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture.
J. Circuits Syst. Comput., 2017

Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Fault-tolerant application specific Network-on-Chip design.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels.
ACM Trans. Archit. Code Optim., 2016

2015
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores.
J. Syst. Archit., 2015

Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes.
J. Syst. Archit., 2015

A constructive heuristic for application mapping onto an express channel based Network-on-Chip.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2014

A locally reconfigurable Network-on-Chip architecture and application mapping onto it.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013
Application-Specific Network-on-Chip synthesis with flexible router Placement.
J. Syst. Archit., 2013

2012
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router.
Microprocess. Microsystems, 2012

2011
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011


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