High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. - Soumya Pandit; Sougata Kar; Chittaranjan A. Mandal; Amit Patra (DATE, 2006)

A formal approach for high level synthesis of linear analog systems. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (ACM Great Lakes Symposium on VLSI, 2006)

A Fast Exploration Procedure for Analog High-Level Specification Translation. - Soumya Pandit; Sumit K. Bhattacharya; Chittaranjan A. Mandal; Amit Patra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Systematic Methodology for High-Level Performance Modeling of Analog Systems. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (VLSI Design, 2009)

An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (Integr., 2010)

Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network. - Sipra Mandal; Soumya Pandit (VLSI Design, 2011)

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (VLSI Design, 2011)

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics. - Joyjit Mukhopadhyay; Soumya Pandit (VLSI Design, 2012)

An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. - Somnath Paul; Abhijit Dana; Soumya Pandit (VDAT, 2013)

Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications. - Debayan Bairagi; Soumya Pandit (VDAT, 2014)

FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection. - Samik Basu 003; Soumya Pandit; Amlan Chakrabarti; Soma Barman Mandal (iSES, 2019)

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. - Subrata Das; Debesh Kumar Das; Soumya Pandit (ACM J. Emerg. Technol. Comput. Syst., 2020)

Minimization of Switching Activity of Graphene Based Circuits. - Subrata Das; Petr Fiser; Soumya Pandit; Debesh Kumar Das (VLSID, 2021)

Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. - Subrata Das; Debesh Kumar Das; Soumya Pandit (VDAT, 2022)

Machine Learning Algorithm for Handwritten Numerical Character Identification Using FPGA Based Custom IP Core. - Shraman Biswas; Soumya Pandit; Arpita Das (TENCON, 2024)

Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters. - Shraman Biswas; Soumya Pandit; Arpita Das (VDAT, 2024)

Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors. - Soumita Chatterjee; Soumya Pandit; Arpita Das (VDAT, 2024)

Coupling of a lightweight model of reduced convolutional autoencoder with linear SVM classifier to detect brain tumours on FPGA. - Soumita Chatterjee; Soumya Pandit; Arpita Das (Expert Syst. Appl., 2025)