Soumyadip Bandyopadhyay

According to our database1, Soumyadip Bandyopadhyay authored at least 14 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
Other 

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Bibliography

2019
Equivalence checking of Petri net models of programs using static and dynamic cut-points.
Acta Inf., 2019

SamaTulyataOne: A Path Based Equivalence Checker.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2018
Analysis of GPGPU Programs for Data-race and Barrier Divergence.
Proceedings of the 13th International Conference on Software Technologies, 2018

2017
An End-to-end Formal Verifier for Parallel Programs.
Proceedings of the 12th International Conference on Software Technologies, 2017

PRESGen: A Fully Automatic Equivalence Checker for Validating Optimizing and Parallelizing Transformations.
Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications, 2017

SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
Proceedings of the Automated Technology for Verification and Analysis, 2017

2016
A Path Construction Algorithm for Translation Validation Using PRES+ Models.
Parallel Processing Letters, 2016

Data-race detection: the missing piece for an end-to-end semantic equivalence checker for parallelizing transformations of array-intensive programs.
Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, 2016

An efficient path based equivalence checking for Petri net based models of programs.
Proceedings of the 9th India Software Engineering Conference, 2016

Implementing an Efficient Path Based Equivalence Checker for Parallel Programs.
Proceedings of the ACM Workshop on Software Engineering Methods for Parallel and High Performance Applications, Kyoto, Japan, May 31, 2016

2015
Validating SPARK: High Level Synthesis Compiler.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
Proceedings of the ICSOFT-EA 2015, 2015

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2012
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012


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