Soumyadip Bandyopadhyay

Orcid: 0000-0001-5865-9754

Affiliations:
  • NVIDIA
  • Hasso Plattner Institute, Potsdam, Germany (former)
  • Birla Institute of Technology & Science, Pilani, Goa, India (former)
  • Indian Institute of Technology, Kharagpur (former)


According to our database1, Soumyadip Bandyopadhyay authored at least 27 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Translation validation of coloured Petri net models of programs on integers.
Acta Informatica, 2022

Solving the instance model-view update problem in AADL.
Proceedings of the 25th International Conference on Model Driven Engineering Languages and Systems, 2022

A Report on the First International Workshop on Program Equivalence (PEQ 2022).
Proceedings of the ISEC 2022: 15th Innovations in Software Engineering Conference, Gandhinagar, India, February 24, 2022

A Comparative Study between ECG-based and PPG-based Heart Rate Monitors for Stress Detection.
Proceedings of the 14th International Conference on COMmunication Systems & NETworkS, 2022

2021
A Report on the Second International Workshop on Software Engineering for Artificial Intelligence (SE4AI 2021).
Proceedings of the ISEC 2021: 14th Innovations in Software Engineering Conference, 2021

Towards an Approach for Translation Validation of Thread-level Parallelizing Transformations using Colored Petri Nets.
Proceedings of the 16th International Conference on Software Technologies, 2021

PNPEq: Verification of Scheduled Conditional Behavior in Embedded Software using Petri Nets.
Proceedings of the 28th Asia-Pacific Software Engineering Conference, 2021

Validating Extended Feature Model Configurations using Petri Nets.
Proceedings of the International Workshop on Petri Nets and Software Engineering 2021 co-located with the 42nd International Conference on Application and Theory of Petri Nets and Concurrency (PETRI NETS 2021), 2021

Translation Validation of Scheduled Conditional Behavior using PN.
Proceedings of the International Workshop on Petri Nets and Software Engineering 2021 co-located with the 42nd International Conference on Application and Theory of Petri Nets and Concurrency (PETRI NETS 2021), 2021

2020
A Report on the First Workshop on Software Engineering for Artificial Intelligence (SE4AI 2020).
Proceedings of the ISEC 2020: 13th Innovations in Software Engineering Conference, 2020

Translation Validation of Loop involving Code Optimizing Transformations using Petri Net based Models of Programs.
Proceedings of the International Workshop on Petri Nets and Software Engineering co-located with 41st International Conference on Application and Theory of Petri Nets and Concurrency (PETRI NETS 2020), 2020

2019
Equivalence checking of Petri net models of programs using static and dynamic cut-points.
Acta Informatica, 2019

SamaTulyataOne: A Path Based Equivalence Checker.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

AES: Automated Evaluation Systems for Computer Programing Course.
Proceedings of the 14th International Conference on Software Technologies, 2019

2018
Analysis of GPGPU Programs for Data-race and Barrier Divergence.
Proceedings of the 13th International Conference on Software Technologies, 2018

2017
An End-to-end Formal Verifier for Parallel Programs.
Proceedings of the 12th International Conference on Software Technologies, 2017

PRESGen: A Fully Automatic Equivalence Checker for Validating Optimizing and Parallelizing Transformations.
Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications, 2017

SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
Proceedings of the Automated Technology for Verification and Analysis, 2017

2016
A Path Construction Algorithm for Translation Validation Using PRES+ Models.
Parallel Process. Lett., 2016

Data-race detection: the missing piece for an end-to-end semantic equivalence checker for parallelizing transformations of array-intensive programs.
Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, 2016

An efficient path based equivalence checking for Petri net based models of programs.
Proceedings of the 9th India Software Engineering Conference, 2016

Implementing an Efficient Path Based Equivalence Checker for Parallel Programs.
Proceedings of the ACM Workshop on Software Engineering Methods for Parallel and High Performance Applications, Kyoto, Japan, May 31, 2016

2015
Validating SPARK: High Level Synthesis Compiler.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
Proceedings of the ICSOFT-EA 2015, 2015

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2012
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2010
Equivalence Checking in Embedded Systems Design Verification using PRES+ model
CoRR, 2010


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