A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply. - Yong-In Park; Soundarapandian Karthikeyan; Frank (Ching-Yuh) Tsay; Eduardo Bartolome (ISCAS (1), 2001)

Digital scheme for quantizer and integrator swing reduction in multibit sigma-delta modulator. - Wern Ming Koe; Franco Maloberti; James R. Hochschild; Soundarapandian Karthikeyan; Yong-In Park (ISCAS, 2006)