A Path Sensitization Technique for Testing of Switched Capacitor Circuits. - Sounil Biswas; Baquer Mazhari (VLSI Design, 2003)

Generalized Sensitization using Fault Tuples. - Sounil Biswas; Kumar N. Dwarakanath; R. D. (Shawn) Blanton (VTS, 2004)

Specification Test Compaction for Analog Circuits and MEMS. - Sounil Biswas; Peng Li 001; R. D. (Shawn) Blanton; Larry T. Pileggi (DATE, 2005)

Statistical Test Compaction Using Binary Decision Trees. - Sounil Biswas; Ronald D. Blanton (IEEE Des. Test Comput., 2006)

Improving the Accuracy of Test Compaction through Adaptive Test Update. - Sounil Biswas; Ronald D. Blanton (ITC, 2008)

Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. - Sounil Biswas; R. D. (Shawn) Blanton (VTS, 2008)

Maintaining Accuracy of Test Compaction through Adaptive Re-learning. - Sounil Biswas; Ronald D. Blanton (VTS, 2009)

Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. - Sounil Biswas; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

An Industrial Study of System-Level Test. - Sounil Biswas; Bruce Cory (IEEE Des. Test Comput., 2012)

Innovative practices session 5C: Machine learning and data analysis in test. - Sounil Biswas; John M. Carulli; Dragoljub Gagi Drmanac; Arpan Bhattacherjee (VTS, 2014)

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. - Sounil Biswas; Hongfei Wang; R. D. (Shawn) Blanton (ACM Trans. Design Autom. Electr. Syst., 2014)

SERDES external loopback test using production parametric-test hardware. - Shalini Arora; Aman Aflaki; Sounil Biswas; Masashi Shimanouchi (ITC, 2016)

A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute Clusters. - Harivinay Kancharla; Sounil Biswas (VLSID, 2025)