Multiple clock domain synchronization for network on chip architectures. - Jabulani Nyathi; Souradip Sarkar; Partha Pratim Pande (SoCC, 2007)

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. - Turbo Majumder; Souradip Sarkar; Partha Pratim Pande; Ananth Kalyanaraman (ASAP, 2010)

Hardware accelerators for biocomputing: A survey. - Souradip Sarkar; Turbo Majumder; Ananth Kalyanaraman; Partha Pratim Pande (ISCAS, 2010)

Network-on-Chip Hardware Accelerators for Biological Sequence Alignment. - Souradip Sarkar; Gaurav Ramesh Kulkarni; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Trans. Computers, 2010)

Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. - Wim Heirman; Trevor E. Carlson; Souradip Sarkar; Pieter Ghysels; Wim Vanroose; Lieven Eeckhout (PARCO, 2011)

Power-aware multi-core simulation for early design stage hardware/software co-optimization. - Wim Heirman; Souradip Sarkar; Trevor E. Carlson; Ibrahim Hur; Lieven Eeckhout (PACT, 2012)

NoC-Based Hardware Accelerator for Breakpoint Phylogeny. - Turbo Majumder; Souradip Sarkar; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Trans. Computers, 2012)

Quater-imaginary base for complex number arithmetic circuits. - Souradip Sarkar; Manil Dev Gomony (DATE, 2018)

Small Transactions with Sustainable Incentives. - Fabio Pianese; Matteo Signorini; Souradip Sarkar (NTMS, 2018)

A Reconfigurable Architecture for Posit Arithmetic. - Souradip Sarkar; Purushotham Murugappa; Manil Dev Gomony (DSD, 2019)

Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers. - Bram Van Bolderik; Souradip Sarkar; Vlado Menkovski; Sonia Heemstra; Manil Dev Gomony (DSD, 2024)