3D vs. 2D analysis of FinFET logic gates under process variations. - Sourindra Chaudhuri; Niraj K. Jha (ICCD, 2011)

Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. - Sourindra Chaudhuri; Prateek Mishra; Niraj K. Jha (VLSI Design, 2012)

FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. - Sourindra Chaudhuri; Niraj K. Jha (VLSID, 2014)

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. - Sourindra Chaudhuri; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. - Sourindra M. Chaudhuri; Prateek Mishra; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. - Sourindra Chaudhuri; Ajay N. Bhoj; Debajit Bhattacharya; Niraj K. Jha (VLSID, 2016)

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. - Sourindra M. Chaudhuri; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2016)