A 9.6 mW/Ch 10 MHz Wide-bandwidth Electrical Impedance Tomography IC with Accurate Phase Compensation for Breast Cancer Detection. - Jaehyuk Lee; Surin Gweon; Kwonjoon Lee; Soyeon Um; Kyoung-Rog Lee; Kwantae Kim; Jihee Lee; Hoi-Jun Yoo (CICC, 2020)

A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection. - Jaehyuk Lee; Surin Gweon; Kwonjoon Lee; Soyeon Um; Kyoung-Rog Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2021)

A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse. - Soyeon Um; Sangyeob Kim; Sangjin Kim; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing. - Sangyeob Kim; Sangjin Kim; Soyeon Um; Soyeon Kim; Kwantae Kim; Hoi-Jun Yoo (HCS, 2022)

A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks. - Wooyoung Jo; Sangjin Kim; Juhyeong Lee; Soyeon Um; Zhiyong Li 016; Hoi-Jun Yoo (ISCAS, 2022)

A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array. - Sangwoo Ha; Sangjin Kim; Donghyeon Han; Soyeon Um; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell. - Soyeon Um; Sangjin Kim; Seongyon Hong; Sangyeob Kim; Hoi-Jun Yoo (A-SSCC, 2023)

A 3.8 mW 1.9 m Ω/√Hz Electrical Impedance Tomography Imaging with 28.4 M Ω High Input Impedance and Loading Calibration. - Soyeon Um; Jaehyuk Lee; Hoi-Jun Yoo (ESSCIRC, 2023)

A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC. - Seongyon Hong; Soyeon Um; Sangjin Kim; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency. - Seryeong Kim; Soyeon Kim; Soyeon Um; Sangjin Kim; Zhiyong Li 016; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration. - Wonhoon Park; Junha Ryu; Sangjin Kim; Soyeon Um; Wooyoung Jo; Sangyoeb Kim; Hoi-Jun Yoo (ISCAS, 2023)

DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (ISSCC, 2023)

Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (VLSI Technology and Circuits, 2023)

Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks. - Sangyeob Kim; Sangjin Kim; Soyeon Um; Soyeon Kim; Kwantae Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2023)

SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit. - Sangyeob Kim; Sangjin Kim; Soyeon Um; Soyeon Kim; Juhyoung Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2023)

NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Sangyeob Kim; Hoi-Jun Yoo (COOL CHIPS, 2024)

Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network. - Sangyeob Kim; Sangjin Kim; Soyeon Um; Soyeon Kim; Hoi-Jun Yoo (ISCAS, 2024)

A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing. - Sunjoo Whang; Soyeon Um; Sangwoo Ha; Hoi-Jun Yoo (ISOCC, 2024)

DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 3.8-mW 1.9-mΩ/√Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer Detect System. - Soyeon Um; Jaehyuk Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell. - Soyeon Um; Sangjin Kim; Seongyon Hong; Sangyeob Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 4.21 TFLOPS/W Memory-Efficient LLM Inference Accelerator with Bit-Layered Non-Uniform Quantization. - Byeongcheol Kim; Sangjin Kim; Sangwoo Ha; Soyeon Um; Kyomin Sohn; Hoi-Jun Yoo (ISCAS, 2025)

A 32.65µm2 Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array. - Jingu Lee; Sangwoo Ha; Sunjoo Whang; Soyeon Kim; Sangjin Kim; Soyeon Um; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2025)

A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator. - Sunjoo Whang; Sangwoo Ha; Soyeon Um; Sangjin Kim; Hoi-Jun Yoo (ISCAS, 2025)

Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI. - Seongyon Hong; Wooyoung Jo; Sangjin Kim; Sangyeob Kim; Soyeon Um; Kyomin Sohn; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2025)