Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. - Spiridon F. Beldianu; Roberto Rojas-Cessa; Eiji Oki; Sotirios G. Ziavras (ICCCN, 2009)

Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. - Spiridon F. Beldianu; Roberto Rojas-Cessa; Eiji Oki; Sotirios G. Ziavras (IEEE Commun. Lett., 2010)

On-chip Vector Coprocessor Sharing for Multicores. - Spiridon F. Beldianu; Sotirios G. Ziavras (PDP, 2011)

Versatile design of shared vector coprocessors for multicores. - Spiridon F. Beldianu; Christopher Dahlberg; Timothy Steele; Sotirios G. Ziavras (Microprocess. Microsystems, 2012)

FPGA and ASIC square root designs for high performance and power efficiency. - Shashank Suresh; Spiridon F. Beldianu; Sotirios G. Ziavras (ASAP, 2013)

Efficient on-chip vector processing for multicore processors. - Spiridon F. Beldianu; Sotirios G. Ziavras (ISSoC, 2013)

Multicore-based vector coprocessor sharing for performance and energy gains. - Spiridon F. Beldianu; Sotirios G. Ziavras (ACM Trans. Embed. Comput. Syst., 2013)

ASIC Design of Shared Vector Accelerators for Multicore Processors. - Spiridon F. Beldianu; Sotirios G. Ziavras (SBAC-PAD, 2014)

Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. - Spiridon F. Beldianu; Sotirios G. Ziavras (IEEE Trans. Computers, 2015)