Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems. - Fillia Makedon; Spyros Tragoudas (WG, 1990)

Circuit partitioning into small sets: a tool to support testing with further applications. - Spyros Tragoudas; R. Farrell; Fillia Makedon (EURO-DAC, 1991)

A comparative study of five language independent programming environments. - Panayiotis E. Pintelas; Spyros Tragoudas (J. Syst. Softw., 1991)

On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. - Dimitrios Kagaris; Fillia Makedon; Spyros Tragoudas (ICCD, 1992)

Searching a Solid Pseudo 3-Sided Orthoconvex Grid. - Antonios Symvonis; Spyros Tragoudas (ISAAC, 1992)

Circuit partitioning into small sets. - Spyros Tragoudas; Fillia Makedon; Robert Farell (Microprocess. Microsystems, 1992)

Approximate solutions for Graph and Hypergraph Partitioning. - Fillia Makedon; Spyros Tragoudas (Algorithmic Aspects of VLSI Layout, 1993)

Partial Scan with Retiming. - Dimitrios Kagaris; Spyros Tragoudas (DAC, 1993)

Minmax-cut graph partitioning problems. - Spyros Tragoudas (Great Lakes Symposium on VLSI, 1993)

Pseudoexhaustive BIST for Sequential Circuits. - Dimitrios Kagaris; Spyros Tragoudas; Dinesh Bhatia (ICCD, 1993)

Searching a Pseudo 3-Sided Solid Orthoconvex Grid. - Antonios Symvonis; Spyros Tragoudas (Int. J. Found. Comput. Sci., 1993)

River routing and density minimization for channels with interchangeable terminals. - Spyros Tragoudas; Ioannis G. Tollis (Integr., 1993)

Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. - Dimitrios Kagaris; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Mathematical model for routability analysis of FPGAs. - Dinesh Bhatia; Amit Chowdhary; Spyros Tragoudas (Great Lakes Symposium on VLSI, 1994)

Retiming algorithms with application to VLSI testability. - Dimitrios Kagaris; Spyros Tragoudas (Great Lakes Symposium on VLSI, 1994)

An improved algorithm for the generalized min-cut partitioning problem. - Spyros Tragoudas (Great Lakes Symposium on VLSI, 1994)

A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. - Dimitrios Kagaris; Spyros Tragoudas (ICCD, 1994)

High Performance Over-the-Cell Routing. - Jim E. Crenshaw; Spyros Tragoudas; Naveed A. Sherwani (VLSI Design, 1994)

A design for testability technique for test pattern generation with LFSRs. - Dimitrios Kagaris; Spyros Tragoudas (VTS, 1994)

The Problem of Partitioning with Duplications and its Applications. - James Haralambides; Spyros Tragoudas (Int. J. Artif. Intell. Tools, 1994)

A method for pseudo-exhaustive test pattern generation. - Dimitrios Kagaris; Fillia Makedon; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On Channel Routing Problems With Interchangeable Terminals. - Spyros Tragoudas (VLSI Design, 1994)

Uniform area timing-driven circuit implementation. - Dimitrios Karayiannis; Spyros Tragoudas (Great Lakes Symposium on VLSI, 1995)

Quickest paths: parallelization and dynamization . - Dimitrios Kagaris; Spyros Tragoudas; Grammati E. Pantziou; Christos D. Zaroliagis (HICSS (2), 1995)

On the Computation of Fast Data Transmissions in Networks with Capacities and Delays. - Dimitrios Kagaris; Spyros Tragoudas; Grammati E. Pantziou; Christos D. Zaroliagis (WADS, 1995)

Avoiding linear dependencies in LFSR test pattern generators. - Dimitrios Kagaris; Spyros Tragoudas (J. Electron. Test., 1995)

Bipartitioning into Overlapping Sets. - James Haralambides; Spyros Tragoudas (Int. J. Found. Comput. Sci., 1995)

Fast Approximation Algorithms for Multicommodity Flow Problems. - Frank Thomson Leighton; Fillia Makedon; Serge A. Plotkin; Clifford Stein 001; Éva Tardos; Spyros Tragoudas (J. Comput. Syst. Sci., 1995)

Pseudo-exhaustive built-in TPG for sequential circuits. - Dimitrios Kagaris; Spyros Tragoudas; Dinesh Bhatia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Deterministic Test Pattern Reproduction by a Counter. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (ED&TC, 1996)

A multiseed counter TPG with performance guarantee. - Dimitrios Kagaris; Spyros Tragoudas (ICCD, 1996)

FPGA Module Minimization. - D. Kuguris; Spyros Tragoudas (ICCD, 1996)

ATPD: An Automatic Test Pattern Generator for Path Delay Faults. - Dimitrios Karayiannis; Spyros Tragoudas (ITC, 1996)

Generating deterministic unordered test patterns with counters. - Dimitrios Kagaris; Spyros Tragoudas (VTS, 1996)

Computing Disjoint Path with Lenght Constraints. - Spyros Tragoudas; Yaakov L. Varol (WG, 1996)

Improved Approximations for the Minimum-Cut Ratio and the Flux. - Spyros Tragoudas (Math. Syst. Theory, 1996)

Retiming-Based Partial Scan. - Dimitrios Kagaris; Spyros Tragoudas (IEEE Trans. Computers, 1996)

On the Use of Counters for Reproducing Deterministic Test Sets. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (IEEE Trans. Computers, 1996)

Min-Cut Partitioning on Underlying Tree and Graph Structures. - Spyros Tragoudas (IEEE Trans. Computers, 1996)

A fast algorithm for minimizing FPGA combinational and sequential modules. - Dimitrios Kagaris; Spyros Tragoudas (ACM Trans. Design Autom. Electr. Syst., 1996)

Cellular automata for generating deterministic test sequences. - Dimitrios Kagaris; Spyros Tragoudas (ED&TC, 1997)

Maximum independent sets on transitive graphs and their applications in testing and CAD. - Dimitrios Kagaris; Spyros Tragoudas (ICCAD, 1997)

Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. - Dimitrios Kagaris; Spyros Tragoudas; Dimitrios Karayiannis (ICCD, 1997)

Implementing and clustering modules with complex delays. - Spyros Tragoudas; Dimitrios Karayiannis (Integr., 1997)

Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. - Dimitrios Kagaris; Spyros Tragoudas; Dimitrios Karayiannis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On-Chip Test Embedding for Multi-Weighted Random LFSRs. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (DFT, 1998)

A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. - Dimitrios Karayiannis; Spyros Tragoudas (VTS, 1998)

Clustering Network Modules with Different Implementations for Delay Minimization. - Dimitrios Karayiannis; Spyros Tragoudas (VLSI Design, 1998)

Timing-Driven Circuit Implementation. - Dimitrios Karayiannis; Spyros Tragoudas (VLSI Design, 1998)

LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. - Dimitrios Kagaris; Spyros Tragoudas (DFT, 1999)

Testing for Path Delay Faults Using Test Points. - Spyros Tragoudas; N. Denny (DFT, 1999)

Functional ATPG for Delay Faults. - Spyros Tragoudas; Maria K. Michael (Great Lakes Symposium on VLSI, 1999)

Embedded cores using built-in mechanisms. - Dimitrios Kagaris; Spyros Tragoudas (ISCAS (1), 1999)

Accurate path delay fault coverage is feasible. - Spyros Tragoudas (ITC, 1999)

Maximum weighted independent sets on transitive graphs and applications1. - Dimitri Kagaris; Spyros Tragoudas (Integr., 1999)

Transmissions in a network with capacities and delays. - Dimitrios Kagaris; Grammati E. Pantziou; Spyros Tragoudas; Christos D. Zaroliagis (Networks, 1999)

On the design of optimal counter-based schemes for test set embedding. - Dimitrios Kagaris; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A fast nonenumerative automatic test pattern generator for pathdelay faults. - Spyros Tragoudas; Dimitrios Karayiannis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Board-level partitioning for partial scan using fuzzy logic. - Spyros Tragoudas; Ralf Münzenberger; Kenneth J. Danhof (IEEE Trans. Fuzzy Syst., 1999)

CAD Tools for BIST/DFT and Delay Faults. - Spyros Tragoudas (The VLSI Handbook, 1999)

Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. - Dimitrios Kagaris; Spyros Tragoudas (ICCD, 2000)

Methods for on-chip embedding of path delay test vectors. - Dimitri Kagaris; Spyros Tragoudas (ISCAS, 2000)

Power dissipation component of a management protocol for ad-hoc networks. - Spyros Tragoudas (WCNC, 2000)

Routing with energy considerations in mobile ad-hoc networks. - Spyros Tragoudas; S. Dimitrova (WCNC, 2000)

Test-set partitioning for multi-weighted random LFSRs. - Dimitri Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (Integr., 2000)

Color Counting and its Application to Path Delay Fault Coverage. - Jayant Deodhar; Spyros Tragoudas (ISQED, 2001)

ATPG for Path Delay Faults without Path Enumeration. - Maria K. Michael; Spyros Tragoudas (ISQED, 2001)

Exact path delay grading with fundamental BDD operations. - Saravanan Padmanaban; Maria K. Michael; Spyros Tragoudas (ITC, 2001)

Computational analysis of counter-based schemes for VLSI test pattern generation. - Dimitrios Kagaris; Spyros Tragoudas (Discret. Appl. Math., 2001)

Von Neumann hybrid cellular automata for generating deterministic test sequences. - Dimitrios Kagaris; Spyros Tragoudas (ACM Trans. Design Autom. Electr. Syst., 2001)

The most reliable data-path transmission. - Spyros Tragoudas (IEEE Trans. Reliab., 2001)

Exact Grading of Multiple Path Delay Faults. - Saravanan Padmanaban; Spyros Tragoudas (DATE, 2002)

An efficient algorithm for finding a path subject to two additive constraints. - Turgay Korkmaz; Marwan Krunz; Spyros Tragoudas (Comput. Commun., 2002)

Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. - Dimitrios Kagaris; Spyros Tragoudas (J. Electron. Test., 2002)

Disjoint Paths with Length Constraints. - Spyros Tragoudas; Yaakov L. Varol (Int. J. Comput. Their Appl., 2002)

On the nonenumerative path delay fault simulation problem. - Dimitrios Kagaris; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A new built-in TPG method for circuits with random patternresistant faults. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

ATPG tools for delay faults at the functional level. - Maria K. Michael; Spyros Tragoudas (ACM Trans. Design Autom. Electr. Syst., 2002)

Non-Enumerative Path Delay Fault Diagnosis . - Saravanan Padmanaban; Spyros Tragoudas (DATE, 2003)

InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. - Dimitri Kagaris; Spyros Tragoudas (IOLTS, 2003)

Generation of Hazard Identification Functions. - Maria K. Michael; Spyros Tragoudas (ISQED, 2003)

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. - Dimitri Kagaris; Spyros Tragoudas (J. Electron. Test., 2003)

Exact path delay fault coverage with fundamental ZBDD operations. - Saravanan Padmanaban; Maria K. Michael; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

An implicit path-delay fault diagnosis methodology. - Saravanan Padmanaban; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Path delay fault testing using test points. - Spyros Tragoudas; N. Denny (ACM Trans. Design Autom. Electr. Syst., 2003)

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. - Saravanan Padmanaban; Spyros Tragoudas (DATE, 2004)

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FCCM, 2004)

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPGA, 2004)

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPL, 2004)

Low power ATPG for path delay faults. - Mahilchi Milir Vaseekar Kumar; Saravanan Padmanaban; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2004)

Security enhancement through multiple path transmission in ad hoc networks. - Themistoklis Haniotakis; Spyros Tragoudas; Constantinos Kalapodas (ICC, 2004)

A high performance data-path to accelerate DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (ICECS, 2004)

Rewiring for Watermarking Digital Circuits. - M. Moiz Khan; Spyros Tragoudas (ISQED, 2004)

An Adaptive Path Delay Fault Diagnosis Methodology. - Saravanan Padmanaban; Spyros Tragoudas (ISQED, 2004)

A Critical Path Selection Method for Delay Testing. - Saravanan Padmanaban; Spyros Tragoudas (ITC, 2004)

On-line Testing Field Programmable Analog Array Circuits. - Haibo Wang 005; Suchitra Kulkarni; Spyros Tragoudas (ITC, 2004)

Compact ATPG for Concurrent SOC Testing. - Arkan Abdulrahman; Spyros Tragoudas (MTV, 2004)

Identification of Gates for Covering all Critical Paths. - M. Moiz Khan; Spyros Tragoudas; Magdy S. Abadir; Jiang Brandon Liu (MTV, 2004)

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (PATMOS, 2004)

A Novel Data-Path for Accelerating DSP Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (SAMOS, 2004)

A unified framework for generating all propagation functions for logic errors and events. - Maria K. Michael; Themistoklis Haniotakis; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Implicit deductive fault simulation for complex delay fault models. - J. V. Deodhar; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Implicit and Exact Path Delay Fault Grading in Sequential Circuits. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (DATE, 2005)

A security protocol for sensor networks. - Khadija Jirari Stewart; Themistoklis Haniotakis; Spyros Tragoudas (GLOBECOM, 2005)

Low power test generation for path delay faults using stability functions. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2005)

Test set enhancement for quality transition faults using function-based methods. - Stelios Neophytou; Maria K. Michael; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2005)

Quality Transition Fault Tests Suitable for Small Delay Defects. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas (ICCD, 2005)

Towards finding path delay fault tests with high test efficiency using ZBDDs. - Maria K. Michael; Kyriakos Christou; Spyros Tragoudas (ICCD, 2005)

Reduced Test Application Time Based on Reachability Analysis. - Themistoklis Haniotakis; Spyros Tragoudas; G. Pani (ISQED, 2005)

Functions for Quality Transition Fault Tests. - Maria K. Michael; Stelios Neophytou; Spyros Tragoudas (ISQED, 2005)

Design and Evaluation of a Security Scheme for Sensor Networks. - Khadija Jirari Stewart; Themistoklis Haniotakis; Spyros Tragoudas (ISQED, 2005)

A Minimum Cut Based Re-Synthesis Approach. - M. Welling; Spyros Tragoudas; Haibo Wang 005 (ISQED, 2005)

A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. - Krishna Prasad Raghuraman; Haibo Wang 005; Spyros Tragoudas (VLSI Design, 2005)

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (J. Circuits Syst. Comput., 2005)

Low Power Test Generation for Path Delay Faults. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas (J. Low Power Electron., 2005)

Rewiring for watermarking digital circuit netlists. - M. Moiz Khan; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Efficient identification of (critical) testable path delay faults using decision diagrams. - Saravanan Padmanaban; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On-chip embedding mechanisms for large sets of vectors for delay test. - Spyros Tragoudas; Vijay Nagarandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Function-based compact test pattern generation for path delay faults. - Maria K. Michael; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Implicit Critical PDF Test Generation with Maximal Test Efficiency. - Kyriakos Christou; Maria K. Michael; Spyros Tragoudas (DFT, 2006)

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. - Sandeep Dechu; Manoj Kumar Goparaju; Spyros Tragoudas (DFT, 2006)

Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. - Stelios Neophytou; Maria K. Michael; Spyros Tragoudas (IOLTS, 2006)

Sub-faults identification for collapsing in diagnosis. - Rajsekhar Adapa; Spyros Tragoudas; Maria K. Michael (ISCAS, 2006)

Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. - Arkan Abdulrahman; Spyros Tragoudas (ISQED, 2006)

Evaluation of Collapsing Methods for Fault Diagnosis. - Rajsekhar Adapa; Spyros Tragoudas; Maria K. Michael (ISQED, 2006)

An Improved Method for Identifying Linear Dependencies in Path Delay Faults. - Edward Flanigan; Themistoklis Haniotakis; Spyros Tragoudas (ISQED, 2006)

Minimizing FPGA Reconfiguration Data at Logic Level. - Krishna Prasad Raghuraman; Haibo Wang 005; Spyros Tragoudas (ISQED, 2006)

Exact At-speed Delay Fault Grading in Sequential Circuits. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (ITC, 2006)

Interconnect Testing for Networks on Chips. - Khadija Jirari Stewart; Spyros Tragoudas (VTS, 2006)

InTeRail: A Test Architecture for Core-Based SOCs. - Dimitri Kagaris; Spyros Tragoudas; Sherin Kuriakose (IEEE Trans. Computers, 2006)

A high-performance data path for synthesizing DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement. - Stelios Neophytou; Maria K. Michael; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Implicit grading of multiple path delay faults. - Saravanan Padmanaban; Spyros Tragoudas (ACM Trans. Design Autom. Electr. Syst., 2006)

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. - Rajsekhar Adapa; Edward Flanigan; Spyros Tragoudas; Michael Laisne; Hailong Cui; Tsvetomir Petrov (ISQED, 2007)

Enhanced Identification of Strong Robustly Testable Paths. - Edward Flanigan; Spyros Tragoudas (ISQED, 2007)

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. - Manoj Kumar Goparaju; Spyros Tragoudas (ISQED, 2007)

Glitch Control with Dynamic Receiver Threshold Adjustment. - Michael N. Skoufis; Haibo Wang 005; Themistoklis Haniotakis; Spyros Tragoudas (ISQED, 2007)

Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. - Edward Flanigan; Rajsekhar Adapa; Hailong Cui; Michael Laisne; Spyros Tragoudas; Tsvetomir Petrov (VLSI Design, 2007)

Accelerating Diagnosis via Dominance Relations between Sets of Faults. - Rajsekhar Adapa; Spyros Tragoudas; Maria K. Michael (VTS, 2007)

Managing the power resources of sensor networks with performance considerations. - Khadija Jirari Stewart; Spyros Tragoudas (Comput. Commun., 2007)

High-Quality Transition Fault ATPG for Small Delay Defects. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Speedups in embedded systems with a high-performance coprocessor datapath. - Michalis D. Galanis; Gregory Dimitroulakos; Spyros Tragoudas; Costas E. Goutis (ACM Trans. Design Autom. Electr. Syst., 2007)

Prioritization of Paths for Diagnosis. - Rajsekhar Adapa; Spyros Tragoudas (DFT, 2008)

A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. - Manoj Kumar Goparaju; Ashok Kumar Palaniswamy; Spyros Tragoudas (DFT, 2008)

Propagation of Transients Along Sensitizable Paths. - Sreenivas Gangadhar; Michael N. Skoufis; Spyros Tragoudas (IOLTS, 2008)

A Novel Test Generation Methodology for Adaptive Diagnosis. - Rajsekhar Adapa; Edward Flanigan; Spyros Tragoudas (ISQED, 2008)

Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. - Edward Flanigan; Arkan Abdulrahman; Spyros Tragoudas (ISQED, 2008)

A High-Performance Bus Architecture for Strongly Coupled Interconnects. - Michael N. Skoufis; Kedar Karmarkar; Themistoklis Haniotakis; Spyros Tragoudas (ISQED, 2008)

Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. - Dheepakkumaran Jayaraman; Edward Flanigan; Spyros Tragoudas (ITC, 2008)

A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. - Manoj Kumar Goparaju; Spyros Tragoudas (VTS, 2008)

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. - Kyriakos Christou; Maria K. Michael; Spyros Tragoudas (J. Electron. Test., 2008)

Low-power multi-core ATPG to target concurrency. - Arkan Abdulrahman; Spyros Tragoudas (Integr., 2008)

Identification of Critical Executable Paths at the Architectural Level. - Chunrong Song; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Graph Theory and Algorithms. - Dimitri Kagaris; Spyros Tragoudas (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. - Edward Flanigan; Spyros Tragoudas; Arkan Abdulrahman (VTS, 2009)

Scalable codeword generation for coupled buses. - Kedar Karmarkar; Spyros Tragoudas (DATE, 2010)

Gating internal nodes to reduce power during scan shift. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)

Scalable identification of threshold logic functions. - Ashok Kumar Palaniswamy; Manoj Kumar Goparaju; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)

Probabilistic methods for the impact of an SET in combinational logic. - Sreenivas Gangadhar; Spyros Tragoudas (IOLTS, 2010)

On-line detection of random voltage perturbations in buses with multiple-threshold receivers. - Michael N. Skoufis; Spyros Tragoudas (IOLTS, 2010)

A novel probabilistic SET propagation method. - Sreenivas Gangadhar; Spyros Tragoudas (ISQED, 2010)

Scan Shift Power Reduction by Gating Internal Nodes. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (J. Low Power Electron., 2010)

A Data Capturing Method for Buses on Chip. - Michael N. Skoufis; Kedar Karmarkar; Spyros Tragoudas; Themistoklis Haniotakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Techniques to Prioritize Paths for Diagnosis. - Rajsekhar Adapa; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Identification of Delay Measurable PDFs Using Linear Dependency Relationships. - Edward Flanigan; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A Scalable Method for Identifying DNA Substrings Using Functions. - Pragyan P. Mohanty; Spyros Tragoudas (BICoB, 2011)

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. - Chandra Babu Dara; Spyros Tragoudas; Themistoklis Haniotakis (DFT, 2011)

A Probabilistic Approach to Diagnose SETs. - Sreenivas Gangadhar; Spyros Tragoudas (DFT, 2011)

Error correction encoding for multi-threshold capture mechanism. - Kedar Karmarkar; Spyros Tragoudas (IOLTS, 2011)

Multi-level secure JTAG architecture. - Luke Pierce; Spyros Tragoudas (IOLTS, 2011)

Occurrence probability analysis of a path at the architectural level. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2011)

An analytical method for estimating SET propagation. - Sreenivas Gangadhar; Spyros Tragoudas (VTS, 2011)

Improved diagnosis using enhanced fault dominance. - Rajsekhar Adapa; Spyros Tragoudas; Maria K. Michael (Integr., 2011)

Accurate calculation of SET propagation probability for hardening. - Sreenivas Gangadhar; Spyros Tragoudas (DFT, 2012)

Transient pulse propagation using the Weibull distribution function. - Adam Watkins; Spyros Tragoudas (DFT, 2012)

A scalable threshold logic synthesis method using ZBDDs. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2012)

Non-enumerative generation of statistical path delays for ATPG. - Ahish Mysore Somashekar; Spyros Tragoudas; Sreenivas Gangadhar; Rathish Jayabharathi (ICCD, 2012)

Delay Analysis for an N-Input Current Mode Threshold Logic Gate. - Chandra Babu Dara; Themistoklis Haniotakis; Spyros Tragoudas (ISVLSI, 2012)

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. - Khadija Jirari Stewart; Themistoklis Haniotakis; Spyros Tragoudas (Ad Hoc Networks, 2012)

An efficient heuristic to identify threshold logic functions. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2012)

An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic. - Michael N. Skoufis; Spyros Tragoudas (IEEE Trans. Computers, 2012)

Low power and high speed current-mode memristor-based TLGs. - Chandra Babu Dara; Themistoklis Haniotakis; Spyros Tragoudas (DFTS, 2013)

Error detection encoding for multi-threshold capture mechanism. - Kedar Karmarkar; Spyros Tragoudas (IOLTS, 2013)

Performance validation through implicit removal of infeasible paths of the behavioral description. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2013)

A method to determine the sensitization probability of a non-robustly testable path. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2013)

Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements. - Ahish Mysore Somashekar; Spyros Tragoudas (ISQED, 2013)

A Probabilistic Approach to Diagnose SETs in Sequential Circuits. - Sreenivas Gangadhar; Spyros Tragoudas (J. Electron. Test., 2013)

Enhanced Secure Architecture for Joint Action Test Group Systems. - Luke Pierce; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Diagnosis of segment delay defects with current sensing. - Wisam Aljubouri; Ahish Mysore Somashekar; Themistoklis Haniotakis; Spyros Tragoudas (DFT, 2014)

ATPG for transition faults of pipelined threshold logic circuits. - Ashok Kumar Palaniswamy; Spyros Tragoudas; Themistoklis Haniotakis (DTIS, 2014)

A novel parallel adaptation of an implicit path delay grading method. - Joseph Lenox; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2014)

Adaptive compressive sensing for low power wireless sensors. - Adam Watkins; Venkata Naresh Mudhireddy; Haibo Wang 005; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2014)

Aging-aware critical paths in deep submicron. - Phaninder Alladi; Spyros Tragoudas (IOLTS, 2014)

Scalable Offline Searches in DNA Sequences. - Pragyan (Sheela) Mohanty; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2014)

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2014)

Nanopipelined threshold network synthesis. - Luke Pierce; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2014)

On-Chip Codeword Generation to Cope With Crosstalk. - Kedar Karmarkar; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Adapting an Implicit Path Delay Grading Method for Parallel Architectures. - Joseph Lenox; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Error Correction Encoding for Tightly Coupled On-Chip Buses. - Kedar Karmarkar; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A BIST approach for counterfeit circuit detection based on NBTI degradation. - Puneet Ramesh Savanur; Phaninder Alladi; Spyros Tragoudas (DFTS, 2015)

Non-enumerative correlation-aware path selection. - Ahish Mysore Somashekar; Spyros Tragoudas; Rathish Jayabharathi (ICCD, 2015)

Towards Trojan circuit detection with maximum state transition exploration. - Joseph Lenox; Spyros Tragoudas (IOLTS, 2015)

Unreachable code identification for improved line coverage. - Luke Pierce; Spyros Tragoudas (ISQED, 2015)

Fast march tests for defects in resistive memory. - Seyed Nima Mozaffari; Spyros Tragoudas; Themistoklis Haniotakis (NANOARCH, 2015)

A Highly Robust Double Node Upset Tolerant latch. - Adam Watkins; Spyros Tragoudas (DFT, 2016)

Identification of delay defects on embedded paths using one current sensor. - Wisam Aljubouri; Spyros Tragoudas; Themistoklis Haniotakis (DTIS, 2016)

Efficient selection of critical paths for delay defects in the presence of process variations. - Phaninder Alladi; Spyros Tragoudas (DTIS, 2016)

An Enhanced Analytical Electrical Masking Model for Multiple Event Transients. - Adam Watkins; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2016)

Compressive image sensor technique with sparse measurement matrix. - Stefan Leitner; Haibo Wang 005; Spyros Tragoudas (SoCC, 2016)

ATPG for Delay Defects in Current Mode Threshold Logic Circuits. - Ashok Kumar Palaniswamy; Spyros Tragoudas; Themistoklis Haniotakis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection. - Ahish Mysore Somashekar; Spyros Tragoudas; Rathish Jayabharathi; Sreenivas Gangadhar (ACM Trans. Design Autom. Electr. Syst., 2016)

A new method to identify threshold logic functions. - Seyed Nima Mozaffari; Spyros Tragoudas; Themistoklis Haniotakis (DATE, 2017)

Efficient Critical Path Selection Under a Probabilistic Delay Model. - Ahish Mysore Somashekar; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2017)

Diagnosis with transition faults on embedded segments. - Theodoros Toulas; Spyros Tragoudas (IOLTS, 2017)

Efficient computation of the sensitization probability of a critical path considering process variations and path correlation. - Pavan Kumar Javvaji; Spyros Tragoudas (ISCAS, 2017)

Reducing power, area, and delay of threshold logic gates considering non-integer weights. - Seyed Nima Mozaffari; Spyros Tragoudas; Themistoklis Haniotakis (ISCAS, 2017)

METS: A multiple event transient simulator. - Adam Watkins; Spyros Tragoudas (ISCAS, 2017)

Aging-aware critical paths for process related validation in the presence of NBTI. - Phaninder Alladi; Spyros Tragoudas (ISQED, 2017)

Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges. - Stefan Leitner; Haibo Wang 005; Spyros Tragoudas (J. Circuits Syst. Comput., 2017)

More Efficient Testing of Metal-Oxide Memristor-Based Memory. - Seyed Nima Mozaffari; Spyros Tragoudas; Themistoklis Haniotakis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements. - Ahish Mysore Somashekar; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Delay Analysis for Current Mode Threshold Logic Gate Designs. - Chandra Babu Dara; Themistoklis Haniotakis; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Method to Model Statistical Path Delays for Accurate Defect Coverage. - Pavan Kumar Javvaji; Spyros Tragoudas (DFT, 2018)

Threshold Voltage Extraction Using Static NBTI Aging. - Puneet Ramesh Savanur; Spyros Tragoudas (DFT, 2018)

Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection. - Pavan Kumar Javvaji; Spyros Tragoudas; Ganesh Kondapuram (ISCAS, 2018)

Test set identification for improved delay defect coverage in the presence of statistical delays. - Pavan Kumar Javvaji; Basim Shanyour; Spyros Tragoudas (ISQED, 2018)

Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors. - Basim Shanyour; Spyros Tragoudas (ITC, 2018)

An Aging Resilient Neural Network Architecture. - Seyed Nima Mozaffari; Krishna Prasad Gnawali; Spyros Tragoudas (NANOARCH, 2018)

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. - Seyed Nima Mozaffari; Spyros Tragoudas; Themistoklis Haniotakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Low Power Artificial Neural Network Architecture. - Krishna Prasad Gnawali; Seyed Nima Mozaffari; Spyros Tragoudas (CoRR, 2019)

On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. - Pavan Kumar Javvaji; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors. - Basim Shanyour; Spyros Tragoudas (IOLTS, 2020)

Radiation Hardened Latch Designs for Double and Triple Node Upsets. - Adam Watkins; Spyros Tragoudas (IEEE Trans. Emerg. Top. Comput., 2020)

Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays. - Pavan Kumar Javvaji; Spyros Tragoudas (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Fault Model to Detect Design Errors in Combinational Circuits. - Puneet Ramesh Savanur; Spyros Tragoudas (DFT, 2021)

Resiliency of SNN on Black-Box Adversarial Attacks. - Bijay Raj Paudel; Aashish Itani; Spyros Tragoudas (ICMLA, 2021)

Predicting YOLO Misdetection by Learning Grid Cell Consensus. - Bijay Raj Paudel; Danushka Senarathna; Haibo Wang 005; Spyros Tragoudas; Yao Hu; Shengbing Jiang (ICMLA, 2021)

Improved CNN classification accuracy with the addition of shallow cascading CNNs. - Vasileios Pentsos; Bijay Raj Paudel; Spyros Tragoudas; Kiriti Nagesh Gowda; Mike Schmit (ICMLA, 2021)

Compressed Learning in MCA Architectures to Tolerate Malicious Noise. - Bijay Raj Paudel; Spyros Tragoudas (IOLTS, 2022)

On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks. - Bijay Raj Paudel; Vasileios Pentsos; Spyros Tragoudas (ISQED, 2022)

Computation of Soft Error Rates Considering Test Pattern Sequences. - Danushka Senarathna; Spyros Tragoudas (ISQED, 2022)

The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays. - Bijay Raj Paudel; Spyros Tragoudas (ITC, 2022)

Improving the Forecasting and Classification of Extreme Events in Imbalanced Time Series Through Block Resampling in the Joint Predictor-Forecast Space. - Xiaoqian Chen; Lalit Gupta; Spyros Tragoudas (IEEE Access, 2022)

High-Speed Memristive Ternary Content Addressable Memory. - Krishna Prasad Gnawali; Spyros Tragoudas (IEEE Trans. Emerg. Top. Comput., 2022)

A statistical approach to improve CNN classification accuracy. - Vasileios Pentsos; Spyros Tragoudas (HPSR, 2023)

Detection and Quantization of Data Drift in Image Classification Neural Networks. - Danushka Senarathna; Spyros Tragoudas; Kiriti Nagesh Gowda; Mike Schmit (HPSR, 2023)

An Enhanced YOLO Failure Detection Method. - Danushka Senarathna; Rezoan Ferdous; Spyros Tragoudas (ICMLA, 2023)

Adversarial Defense using Memristors and Input Preprocessing *. - Bijay Raj Paudel; Spyros Tragoudas (ISCAS, 2023)

High Precision Winner-Take-All Circuit for Neural Networks. - Bijay Raj Paudel; Haibo Wang 005; Spyros Tragoudas; Omkar Rijal (SOCC, 2023)

Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation. - Danushka Senarathna; Spyros Tragoudas (SOCC, 2023)

Enhanced Distribution Matching for Multiclass Quantification. - Danuka Malinda; Danushka Senarathna; Spyros Tragoudas (ICMLA, 2024)

Memristive Crossbar Array-Based Adversarial Defense Using Compression. - Bijay Raj Paudel; Spyros Tragoudas (IEEE Trans. Emerg. Top. Comput., 2024)

Energy-Aware DNN Task Scheduling with Dynamic Batching and Frequency Adjustment. - Vasileios Pentsos; Spyros Tragoudas; Kiriti Nagesh Gowda; Mike Schmit (ISQED, 2025)

A Hybrid LSTM-Transformer Model for Power Load Forecasting. - Vasileios Pentsos; Spyros Tragoudas; Jason Wibbenmeyer; Nasser Khdeer (IEEE Trans. Smart Grid, 2025)

A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers. - Aikaterini Maria Panteleaki; Varatheepan Paramanayakam; Vasileios Pentsos; Andreas Karatzas; Spyros Tragoudas; Iraklis Anagnostopoulos (CoRR, 2025)