A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis. - Rajat Subhra Chakraborty; Samuel Pagliarini; Jimson Mathew; Sree Ranjani Rajendran; M. Nirmala Devi 001 (IEEE Trans. Emerg. Top. Comput., 2017)

A Novel Logical Locking Technique Against Key-Guessing Attacks. - Sree Ranjani Rajendran; M. Nirmala Devi 001 (ISED, 2018)

Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks. - Sree Ranjani Rajendran; M. Nirmala Devi 001 (VDAT, 2018)

SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection. - Sree Ranjani Rajendran; Rijoy Mukherjee; Rajat Subhra Chakraborty (ASHES@CCS, 2020)

KARNA for a Trustable Hardware. - Sree Ranjani Rajendran (VDAT, 2020)

Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. - Vishnu Bajjuri; Nalesh S 001; Sree Ranjani Rajendran; S. Kala (iSES, 2022)

A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention. - Rijoy Mukherjee; Sree Ranjani Rajendran; Rajat Subhra Chakraborty (J. Cryptogr. Eng., 2022)

HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities. - Sree Ranjani Rajendran; Shams Tarek; Benjamin M. Hicks; Hadi Mardani Kamali; Farimah Farahmandi; Mark Tehranipoor (DATE, 2023)

Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough. - Shams Tarek; Hasan Al Shaikh; Sree Ranjani Rajendran; Farimah Farahmandi (ISVLSI, 2023)

CAD Tools Pathway in Hardware Security. - Sree Ranjani Rajendran; Farimah Farahmandi; Mark Tehranipoor (VLSID, 2024)

Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software. - Sree Ranjani Rajendran; Nusrat Farzana Dipu; Shams Tarek; Hadi Mardani Kamali; Farimah Farahmandi; Mark Tehranipoor (IEEE Trans. Inf. Forensics Secur., 2024)

Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes. - Senthil Murugan; Ramesh Bhakthavatchalu; Karthi Balasubramanian; B. Yamuna; Deepak Mishra; Sree Ranjani Rajendran (IEEE Access, 2025)

Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification: A Survey. - Imed Ben Dhaou; Syhem Larguech; Sree Ranjani Rajendran; Rajat Subhra Chakraborty; Hannu Tenhunen; Ahmed Abdelgawad 001 (Found. Trends Electron. Des. Autom., 2025)