On the Computation of Detection Probability for Multiple Faults. - Sreejit Chakravarty; Harry B. Hunt III (ITC, 1986)

A Unified Approach to Designing Fault-Tolerant Processor Ensembles. - Sreejit Chakravarty; Shambhu J. Upadhyaya (ICPP (1), 1988)

A Testable Realization of CMOS Combinational Circuits. - Sreejit Chakravarty (ITC, 1989)

A Note on Detecting Sneak Paths in Transistor Networks. - Sreejit Chakravarty; Harry B. Hunt III (IEEE Trans. Computers, 1989)

The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. - Sreejit Chakravarty; Harry B. Hunt III; S. S. Ravi; Daniel J. Rosenkrantz (IEEE Trans. Computers, 1989)

On the complexity of computing tests for CMOS gates. - Sreejit Chakravarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). - Sreejit Chakravarty (DAC, 1990)

Heuristics for the MSC Problem for Serial and Shared-Memory Computers. - Ajay Shekhawat; Sreejit Chakravarty (ICPP (3), 1990)

Testing of non-feedback bridging faults. - Sreejit Chakravarty (Integr., 1990)

On Computing Signal Probability and Detection Probability of Stuck-at Faults. - Sreejit Chakravarty; Harry B. Hunt III (IEEE Trans. Computers, 1990)

Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. - Sreejit Chakravarty; S. S. Ravi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A characterization of robust test-pairs for stuck-open faults. - Sreejit Chakravarty (J. Electron. Test., 1991)

Minimum area layout of series-parallel transistor networks is NP-hard. - Sreejit Chakravarty; Xin He; S. S. Ravi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. - Sreejit Chakravarty; Minsheng Liu (DAC, 1992)

On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets. - Sreejit Chakravarty (VLSI Design, 1992)

Algorithms for IDDQ measurement based diagnosis of bridging faults. - Sreejit Chakravarty; Minsheng Liu (J. Electron. Test., 1992)

Parallel and serial heuristics for the minimum set cover problem. - Sreejit Chakravarty; Ajay Shekhawat (J. Supercomput., 1992)

An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. - Sreejit Chakravarty; Yiming Gong (DAC, 1993)

Simulation and generation of IDDQ tests for bridging faults in combinational circuits. - Sreejit Chakravarty; Paul J. Thadikaran (VTS, 1993)

A Characterization of Binary Decision Diagrams. - Sreejit Chakravarty (IEEE Trans. Computers, 1993)

A Study of IDDQ Subset Selection Algorithms for Bridging Faults. - Sreejit Chakravarty; Paul J. Thadikaran (ITC, 1994)

IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. - Sreejit Chakravarty; Sivaprakasam Suresh (VLSI Design, 1994)

Diagnostic simulation of stuck-at faults in combinational circuits. - Sreejit Chakravarty; Yiming Gong (VTS, 1994)

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. - Srikanth Venkataraman; Ismed Hartanto; W. Kent Fuchs; Elizabeth M. Rudnick; Sreejit Chakravarty; Janak H. Patel (DAC, 1995)

Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. - Paul J. Thadikaran; Sreejit Chakravarty; Janak H. Patel (FTCS, 1995)

On adaptive diagnostic test generation. - Yiming Gong; Sreejit Chakravarty (ICCAD, 1995)

Voting model based diagnosis of bridging faults in combinational circuits. - Sreejit Chakravarty; Yiming Gong (VLSI Design, 1995)

Cyclic stress tests for full scan circuits. - Vinay Dabholkar; Sreejit Chakravarty; J. Najm; Janak H. Patel (VTS, 1995)

Conference Reports. - Sreejit Chakravarty; Ramalingam Sridhar; Shambhu J. Upadhyaya; Yervant Zorian; Gil Philips; Bozena Kaminska; Bernard Courtois (IEEE Des. Test Comput., 1995)

Fast Algorithms for Computer IDDQ Tests for Combination Circuits. - Paul J. Thadikaran; Sreejit Chakravarty (VLSI Design, 1996)

A sampling technique for diagnostic fault simulation. - Sreejit Chakravarty (VTS, 1996)

Diagnostic simulation of stuck-at faults in combinational circuits. - Sreejit Chakravarty; Yiming Gong; Srikanth Venkataraman (J. Electron. Test., 1996)

Algorithms to select IDDQ measurement points to detect bridging faults. - Sreejit Chakravarty; Paul J. Thadikaran (J. Electron. Test., 1996)

A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. - Sreejit Chakravarty (IEEE Trans. Computers, 1996)

Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. - Sreejit Chakravarty; Paul J. Thadikaran (IEEE Trans. Computers, 1996)

On the capability of delay tests to detect bridges and opens. - Sreejit Chakravarty (Asian Test Symposium, 1997)

Computing stress tests for interconnect defects. - Vinay Dabholkar; Sreejit Chakravarty (Asian Test Symposium, 1997)

Using fault sampling to compute IDDQ diagnostic test set. - Yiming Gong; Sreejit Chakravarty (VTS, 1997)

Algorithms to compute bridging fault coverage of IDDQ test sets. - Paul J. Thadikaran; Sreejit Chakravarty; Janak H. Patel (ACM Trans. Design Autom. Electr. Syst., 1997)

A new framework for generating optimal March tests for memory arrays. - Kamran Zarrineh; Shambhu J. Upadhyaya; Sreejit Chakravarty (ITC, 1998)

Computing Stress Tests for Gate Oxide Shorts. - Vinay Dabholkar; Sreejit Chakravarty (VLSI Design, 1998)

Techniques for minimizing power dissipation in scan and combinational circuits during test application. - Vinay Dabholkar; Sreejit Chakravarty; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Locating bridging faults using dynamically computed stuck-at fault dictionaries. - Yiming Gong; Sreejit Chakravarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

On Detecting Bridges Causing Timing Failures. - Sreenivas Mandava; Sreejit Chakravarty; Sandip Kundu (ICCD, 1999)

A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. - Sujit T. Zachariah; Sreejit Chakravarty (VLSI Design, 1999)

Techniques to Encode and Compress Fault Dictionaries. - Sreejit Chakravarty; Vinodh Gopal (VTS, 1999)

A novel algorithm to extract two-node bridges. - Sujit T. Zachariah; Sreejit Chakravarty; Carl D. Roth (DAC, 2000)

An analysis of the delay defect detection capability of the ECR test method. - Seonki Kim; Sreejit Chakravarty; Bapiraju Vinnakota (ITC, 2000)

A scalable and efficient methodology to extract two node bridges from large industrial circuits. - Sujit T. Zachariah; Sreejit Chakravarty (ITC, 2000)

STBM: a fast algorithm to simulate IDDQ tests forleakage faults. - Sreejit Chakravarty; Sujit T. Zachariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. - Sujit T. Zachariah; Sreejit Chakravarty (VLSI Design, 2001)

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. - Ismed Hartanto; Srikanth Venkataraman; W. Kent Fuchs; Elizabeth M. Rudnick; Janak H. Patel; Sreejit Chakravarty (ACM Trans. Design Autom. Electr. Syst., 2001)

Automatic generation and compaction of March tests for memory arrays. - Kamran Zarrineh; Shambhu J. Upadhyaya; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Novel ATPG algorithms for transition faults. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ETW, 2002)

Supplemental Test Methods (Tutorial Abstract). - Sreejit Chakravarty (ISQED, 2002)

Experimental Evaluation of Scan Tests for Bridges. - Sreejit Chakravarty; Ankur Jain; Nandakumar Radhakrishnan; Eric W. Savage; Sujit T. Zachariah (ITC, 2002)

Techniques to Reduce Data Volume and Application Time for Transition Test. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ITC, 2002)

Fault Models for Speed Failures Caused by Bridges and Opens. - Sreejit Chakravarty; Ankur Jain (VTS, 2002)

Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. - Sreejit Chakravarty; Kambiz Komeyli; Eric W. Savage; Michael J. Carruthers; Bret T. Stastny; Sujit T. Zachariah (VTS, 2002)

Efficient Implication - Based Untestable Bridge Fault Identifier. - Manan Syal; Michael S. Hsiao; Kiran B. Doreswamy; Sreejit Chakravarty (VTS, 2003)

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (J. Electron. Test., 2003)

Algorithm to extract two-node bridges. - Sujit T. Zachariah; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Defect Coverage Analysis of Partitioned Testing. - Sreejit Chakravarty; Eric W. Savage; Eric N. Tran (ITC, 2004)

Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. - Manan Syal; Michael S. Hsiao; Sreejit Chakravarty (ITC, 2004)

Extraction of two-node bridges from large industrial circuits. - Sujit T. Zachariah; Sreejit Chakravarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Improving Logic Test Quality of Microprocessors. - Sreejit Chakravarty (Asian Test Symposium, 2005)

Untestable Multi-Cycle Path Delay Faults in Industrial Designs. - Manan Syal; Michael S. Hsiao; Suriyaprakash Natarajan; Sreejit Chakravarty (Asian Test Symposium, 2005)

Implicit and Exact Path Delay Fault Grading in Sequential Circuits. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (DATE, 2005)

Logic proximity bridges. - Eric N. Tran; Vamsee Krishna; Sujit T. Zachariah; Sreejit Chakravarty (ITC, 2005)

Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. - Sreejit Chakravarty; Yi-Shing Chang; Hiep Hoang; Sridhar Jayaraman; Silvio Picano; Cheryl Prunty; Eric W. Savage; Rehan Sheikh; Eric N. Tran; Khen Wee (VTS, 2005)

Transition Tests for High Performance Microprocessors. - Yi-Shing Chang; Sreejit Chakravarty; Hiep Hoang; Nick Thorpe; Khen Wee (VTS, 2005)

Efficient techniques for transition testing. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ACM Trans. Design Autom. Electr. Syst., 2005)

An Approach to Minimizing Functional Constraints. - Abhijit Jas; Yi-Shing Chang; Sreejit Chakravarty (DFT, 2006)

Exact At-speed Delay Fault Grading in Sequential Circuits. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (ITC, 2006)

A Study of Implication Based Pseudo Functional Testing. - Manan Syal; Kameshwar Chandrasekar; Vishnu C. Vimjam; Michael S. Hsiao; Yi-Shing Chang; Sreejit Chakravarty (ITC, 2006)

Path Delay Fault Simulation on Large Industrial Designs. - Suriyaprakash Natarajan; Srinivas Patil; Sreejit Chakravarty (VTS, 2006)

Silicon Evaluation of Logic Proximity Bridge Patterns. - Eric N. Tran; Vishwashanth Kasulasrinivas; Sreejit Chakravarty (VTS, 2006)

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. - Mahilchi Milir Vaseekar Kumar; Spyros Tragoudas; Sreejit Chakravarty; Rathish Jayabharathi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay. - Sean H. Wu; Sreejit Chakravarty; Alexander Tetelbaum; Li-C. Wang (ATS, 2008)

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

An Enhanced Logic BIST Architecture for Online Testing. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2008)

Detection of Internal Stuck-open Faults in Scan Chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2008)

An Industrial Case Study of Sticky Path-Delay Faults. - I-De Huang; Yi-Shing Chang; Sandeep K. Gupta 001; Sreejit Chakravarty (VTS, 2008)

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (VTS, 2008)

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. - Abhijit Jas; Yi-Shing Chang; Sreejit Chakravarty (J. Electron. Test., 2008)

Path selection for monitoring unexpected systematic timing effects. - Nicholas Callegari; Pouria Bastani; Li-C. Wang; Sreejit Chakravarty; Alexander Tetelbaum (ASP-DAC, 2009)

Detectability of internal bridging faults in scan chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2009)

Improving the Detectability of Resistive Open Faults in Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2009)

Forecasting Stock Market Indices using Hybrid Network. - Sreejit Chakravarty; Pradipta K. Dash (NaBIC, 2009)

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. - Loganathan Lingappan; Vijay Gangaram; Niraj K. Jha; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Modified Scan Flip-Flop for Low Power Testing. - Amit Mishra 002; Nidhi Sinha; Satdev; Virendra Singh; Sreejit Chakravarty; Adit D. Singh (Asian Test Symposium, 2010)

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. - Wei Zhao 010; Junxia Ma; Mohammad Tehranipoor; Sreejit Chakravarty (Asian Test Symposium, 2010)

Testing of latch based embedded arrays using scan tests. - Fan Yang 060; Sreejit Chakravarty (ITC, 2010)

Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. - Sreejit Chakravarty (VTS, 2010)

Impact of multiple input switching on delay test under process variation. - Sean H. Wu; Sreejit Chakravarty; Li-C. Wang (VTS, 2010)

A Process Monitor Based Speed Binning and Die Matching Algorithm. - Sreejit Chakravarty (Asian Test Symposium, 2011)

Optimal manufacturing flow to determine minumum operating voltage. - Sreejit Chakravarty; Binh Dang; Darcy Escovedo; A. J. Haas (ITC, 2011)

Power-safe test application using an effective gating approach considering current limits. - Wei Zhao 010; Mohammad Tehranipoor; Sreejit Chakravarty (VTS, 2011)

Dynamic filter weights neural network model integrated with differential evolution for day-ahead price forecasting in energy market. - Sreejit Chakravarty; Pradipta K. Dash (Expert Syst. Appl., 2011)

An Evolutionary Functional Link Neural Fuzzy Model for Financial Time Series Forecasting. - Sreejit Chakravarty; Pradipta K. Dash; V. Ravikumar Pandi; Bijaya K. Panigrahi (Int. J. Appl. Evol. Comput., 2011)

Silicon evaluation of faster than at-speed transition delay tests. - Sreejit Chakravarty; Narendra Devta-Prasanna; Arun Gunda; Junxia Ma; Fan Yang 060; H. Guo; R. Lai; D. Li (VTS, 2012)

A novel method for fast identification of peak current during test. - Wei Zhao 010; Sreejit Chakravarty; Junxia Ma; Narendra Devta-Prasanna; Fan Yang 060; Mohammad Tehranipoor (VTS, 2012)

A PSO based integrated functional link net and interval type-2 fuzzy logic system for predicting stock market indices. - Sreejit Chakravarty; Pradipta K. Dash (Appl. Soft Comput., 2012)

Evolutionary functional link interval type-2 fuzzy neural system for exchange rate prediction. - Sreejit Chakravarty; Pradipta K. Dash (Int. J. Data Min. Model. Manag., 2012)

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. - Hassan Salmani; Wei Zhao 010; Mohammad Tehranipoor; Sreejit Chakravarty; Patrick Girard 001; Xiaoqing Wen (J. Low Power Electron., 2012)

Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits. - Wei Zhao 010; Mohammad Tehranipoor; Sreejit Chakravarty (J. Low Power Electron., 2012)

Innovative practices session 2C: Memory test. - Charutosh Dixit; Ramesh C. Tekumalla; Sreejit Chakravarty; Manuel d'Abreu; Zhuoyu Bao; Concetta Riccobene (VTS, 2013)

Power-safe application of tdf patterns to flip-chip designs during wafer test. - Wei Zhao 010; Junxia Ma; Mohammad Tehranipoor; Sreejit Chakravarty (ACM Trans. Design Autom. Electr. Syst., 2013)

Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests. - Fan Yang 060; Sreejit Chakravarty; Arun Gunda; Nicole Wu; Jianyu Ning (ATS, 2014)

An improved cuckoo search based extreme learning machine for medical data classification. - P. Mohapatra; Sreejit Chakravarty; Pradipta K. Dash (Swarm Evol. Comput., 2015)

A Hybrid Kernel Extreme Learning Machine and Improved Cat Swarm Optimization for Microarray Medical Data Classification. - Sreejit Chakravarty; Ranjeeta Bisoi; P. K. Dash (Int. J. Appl. Evol. Comput., 2016)

Evolutionary extreme learning machine for energy price forecasting. - Sreejit Chakravarty; P. Mohapatra; Pradipta Kishore Dash (Int. J. Knowl. Based Intell. Eng. Syst., 2016)

Microarray medical data classification using kernel ridge regression and modified cat swarm optimization based gene selection system. - P. Mohapatra; Sreejit Chakravarty; P. K. Dash (Swarm Evol. Comput., 2016)

Innovative practices session 6C DFT for functional safety. - Prashant Goteti; Sreejit Chakravarty (VTS, 2017)

A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing. - Sourav Das 002; Fei Su; Sreejit Chakravarty (ITC, 2018)

Innovative practices on memory test practice. - M. Casarsa; Gurgen Harutyunyan; Kaitlyn Chen; Ramesh Sharma; Giri Podichetty; Martin Keim; Sreejit Chakravarty; Ramesh C. Tekumalla (VTS, 2018)

Innovative practices on functional testing and fault simulation for FuSa. - Anandh Krishnan; John van Gelder; Mayukh Bhattacharya; Sreejit Chakravarty; Prashant Goteti (VTS, 2018)

A Comparative Study of Pre-bond TSV Test Methodologies. - Sourav Das 002; Fei Su; Sreejit Chakravarty (VTS, 2019)

Internal I/O Testing: Definition and a Solution. - Sreejit Chakravarty; Fei Su; Indira A. Gohad; Sudheer V. Bandana; B. S. Adithya; Wei Ming Lim (VTS, 2020)

Testing of Prebond Through Silicon Vias. - Sourav Das 002; Fei Su; Sreejit Chakravarty (IEEE Des. Test, 2020)

Special Session: A Call to Standardize Chip-let Interconnect Testing. - Sreejit Chakravarty (VTS, 2022)

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Slimane Boutobza; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (3DIC, 2023)

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (VTS, 2023)

Silent Data Errors: Sources, Detection, and Modeling. - Adit D. Singh; Sreejit Chakravarty; George Papadimitriou 001; Dimitris Gizopoulos (VTS, 2023)

IP Session on Chiplet: Design, Assembly, and Test. - Bapi Vinnakota; Jaber Derakhshandeh; Eric Beyne; Erik Jan Marinissen; Sreejit Chakravarty (VTS, 2023)