Srenik S. Mehta

According to our database1, Srenik S. Mehta authored at least 12 papers between 2002 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011

2010
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC.
IEEE J. Solid State Circuits, 2010

A calibration-free 800MHz fractional-N digital PLL with embedded TDC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Design and implementation of a CMO 802.11n SoC.
IEEE Commun. Mag., 2009

A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN.
IEEE J. Solid State Circuits, 2008


2006
A 1.9-GHz Single-Chip CMOS PHS Cellphone.
IEEE J. Solid State Circuits, 2006

A 1.9GHz Single-Chip CMOS PHS Cellphone.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
An 802.11g WLAN SoC.
IEEE J. Solid State Circuits, 2005

2004
A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN.
IEEE J. Solid State Circuits, 2004

2002
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems.
IEEE J. Solid State Circuits, 2002


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