Dual pillar spin-transfer torque MRAMs for low power applications. - Niladri Narayan Mojumder; Xuanyao Fong; Charles Augustine; Sumeet Kumar Gupta; Sri Harsha Choday; Kaushik Roy 001 (ACM J. Emerg. Technol. Comput. Syst., 2013)

Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting. - Sri Harsha Choday; Kon-Woo Kwon; Kaushik Roy 001 (ICCAD, 2014)

Spin Orbit Torque Based Electronic Neuron. - Abhronil Sengupta; Sri Harsha Choday; Yusung Kim 002; Kaushik Roy 001 (CoRR, 2014)

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. - Xuanyao Fong; Yusung Kim 002; Sri Harsha Choday; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. - Kon-Woo Kwon; Sri Harsha Choday; Yusung Kim 002; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Spin-Transfer Torque Memories: Devices, Circuits, and Systems. - Xuanyao Fong; Yusung Kim 002; Rangharajan Venkatesan; Sri Harsha Choday; Anand Raghunathan; Kaushik Roy 001 (Proc. IEEE, 2016)

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. - Mike Davies 002; Narayan Srinivasa; Tsung-Han Lin; Gautham N. Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios D. Dimou; Prasad Joshi; Nabil Imam; Shweta Jain 005; Yuyun Liao; Chit-Kwan Lin; et al. (IEEE Micro, 2018)