SPOT: A computer aided digital design system - Sridevan Parameswaran (1991)

Design automation of self checking circuits. - Sayed Mohammad Kia; Sri Parameswaran (EURO-DAC, 1994)

Novel architectures for TSC/CD and SFS/SCD synchronous controllers. - Sayed Mohammad Kia; Sri Parameswaran (VTS, 1994)

Reclocking for high-level synthesis. - Pradip K. Jha; Nikil D. Dutt; Sri Parameswaran (ASP-DAC, 1995)

Profiling in the ASP codesign environment. - Matthew F. Parkinson; Sri Parameswaran (ISSS, 1995)

Power consumption in CMOS combinational logic blocks at high frequencies. - Sri Parameswaran; Hui Guo 001 (ASP-DAC, 1997)

Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. - Hui Guo 001; Sri Parameswaran (ASP-DAC, 1998)

HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). - Sri Parameswaran (ASP-DAC, 1998)

Power Reduction in Pipelines. - Sri Parameswaran; Hui Guo 001 (ASP-DAC, 1998)

Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. - Allan Rae; Sri Parameswaran (ISSS, 1998)

Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. - Allan Rae; Sri Parameswaran (ASP-DAC, 2000)

High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. - Vince E. Boros; Aleksandar D. Rakic; Sri Parameswaran (DAC, 2000)

Profiling in the ASP codesign environment. - Sri Parameswaran; Matthew F. Parkinson; Peter L. Bartlett (J. Syst. Archit., 2000)

Code placement in hardware/software co-synthesis to improve performance and reduce cost. - Sri Parameswaran (DATE, 2001)

I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. - Sri Parameswaran; Jörg Henkel (ICCAD, 2001)

SWASAD: An ASIC Design for High Speed DNA Sequence Matching. - Tony Han; Sri Parameswaran (ASP-DAC/VLSI Design, 2002)

Rapid Configuration & Instruction Selection for an ASIP: A Case Study. - Newton Cheung; Jörg Henkel; Sri Parameswaran (Embedded Software for SoC, 2003)

Multi-parametric improvements for embedded systems using code-placement and address bus coding. - Sri Parameswaran; Jörg Henkel; Haris Lekatsas (ASP-DAC, 2003)

Rapid Configuration and Instruction Selection for an ASIP: A Case Study. - Newton Cheung; Jörg Henkel; Sri Parameswaran (DATE, 2003)

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. - Newton Cheung; Sri Parameswaran; Jörg Henkel (ICCAD, 2003)

Specification and Design of Multi-Million Gate SOCs. - Ramesh Chandra; Preeti Ranjan Panda; Jörg Henkel; Sri Parameswaran; Loganath Ramachandran (VLSI Design, 2003)

Dual-pipeline heterogeneous ASIP design. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (CODES+ISSS, 2004)

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. - Newton Cheung; Sri Parameswaran; Jörg Henkel; Jeremy Chan (DATE, 2004)

A quantitative study and estimation models for extensible instructions in embedded processors. - Newton Cheung; Sri Parameswaran; Jörg Henkel (ICCAD, 2004)

Hardware/software managed scratchpad memory for embedded system. - Andhi Janapsatya; Sri Parameswaran; Aleksandar Ignjatovic (ICCAD, 2004)

NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. - Jeremy Chan; Sri Parameswaran (VLSI Design, 2004)

Battery-aware instruction generation for embedded processors. - Newton Cheung; Sri Parameswaran; Jörg Henkel (ASP-DAC, 2005)

Micro embedded monitoring for security in application specific instruction-set processors. - Roshan G. Ragel; Sri Parameswaran; Sayed Mohammad Kia (CASES, 2005)

Novel architecture for loop acceleration: a case study. - Seng Lin Shee; Sri Parameswaran; Newton Cheung (CODES+ISSS, 2005)

NoCEE: energy macro-model extraction methodology for network on chip routers. - Jeremy Chan; Sri Parameswaran (ICCAD, 2005)

Balancing System Level Pipelines with Stage Voltage Scaling. - Hui Guo 001; Sri Parameswaran (ISVLSI, 2005)

Rapid Embedded Hardware/Software System Generation. - Jorgen Peddersen; Seng Lin Shee; Andhi Janapsatya; Sri Parameswaran (VLSI Design, 2005)

The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (WCNC, 2005)

Instruction code mapping for performance increase and energy reduction in embedded computer systems. - Sri Parameswaran; Jörg Henkel (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A novel instruction scratchpad memory optimization method based on concomitance metric. - Andhi Janapsatya; Aleksandar Ignjatovic; Sri Parameswaran (ASP-DAC, 2006)

Finding optimal L1 cache configuration for embedded systems. - Andhi Janapsatya; Aleksandar Ignjatovic; Sri Parameswaran (ASP-DAC, 2006)

Application specific forwarding network and instruction encoding for multi-pipe ASIPs. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (CODES+ISSS, 2006)

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. - Roshan G. Ragel; Sri Parameswaran (CODES+ISSS, 2006)

Heterogeneous multiprocessor implementations for JPEG: : a case study. - Seng Lin Shee; Andrea Erdos; Sri Parameswaran (CODES+ISSS, 2006)

IMPRES: integrated monitoring for processor reliability and security. - Roshan G. Ragel; Sri Parameswaran (DAC, 2006)

Customization of application specific heterogeneous multi-pipeline processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (DATE, 2006)

Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor. - Hui Wu 001; Sridevan Parameswaran (EUC, 2006)

ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (VLSI Design, 2006)

Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. - Andhi Janapsatya; Aleksandar Ignjatovic; Sri Parameswaran (IEEE Trans. Very Large Scale Integr. Syst., 2006)

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. - Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2007)

A smart random code injection to mask power analysis based side channel attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (CODES+ISSS, 2007)

Ensuring secure program execution in multiprocessor embedded systems: a case study. - Krutartha Patel; Sridevan Parameswaran; Seng Lin Shee (CODES+ISSS, 2007)

RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (DAC, 2007)

Design Methodology for Pipelined Heterogeneous Multiprocessor System. - Seng Lin Shee; Sri Parameswaran (DAC, 2007)

Automatic application specific floating-point unit generation. - Yee Jern Chong; Sri Parameswaran (DATE, 2007)

Instruction trace compression for rapid instruction cache simulation. - Andhi Janapsatya; Aleksandar Ignjatovic; Sri Parameswaran; Jörg Henkel (DATE, 2007)

Energy Driven Application SelfAdaptation. - Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2007)

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. - Jeremy Chan; Sri Parameswaran (ASP-DAC, 2008)

Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. - Haris Javaid; Sri Parameswaran (CODES+ISSS, 2008)

LOCS: a low overhead profiler-driven design flow for security of MPSoCs. - Krutartha Patel; Sri Parameswaran (CODES+ISSS, 2008)

Rapid application specific floating-point unit generation with bit-alignment. - Yee Jern Chong; Sri Parameswaran (DAC, 2008)

SHIELD: a software hardware design methodology for security and reliability of MPSoCs. - Krutartha Patel; Sri Parameswaran (DAC, 2008)

A Formal Approach To The Protocol Converter Problem. - Karin Avnit; Vijay D'Silva; Arcot Sowmya; S. Ramesh; Sri Parameswaran (DATE, 2008)

MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. - Jude Angelo Ambrose; Sri Parameswaran; Aleksandar Ignjatovic (ICCAD, 2008)

Anatomy of Differential Power Analysis for AES. - Jude Angelo Ambrose; Naeill Aldon; Aleksandar Ignjatovic; Sri Parameswaran (SYNASC, 2008)

Embedded systems security - an overview. - Sri Parameswaran; Tilman Wolf (Des. Autom. Embed. Syst., 2008)

Guest editorial for special issue on embedded system security. - Tilman Wolf; Sri Parameswaran (Des. Autom. Embed. Syst., 2008)

Low-Impact Processor for Dynamic Runtime Power Management. - Jorgen Peddersen; Sri Parameswaran (IEEE Des. Test Comput., 2008)

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. - Seng Lin Shee; Andrea Erdos; Sri Parameswaran (Int. J. Parallel Program., 2008)

Energy Driven Application Self-Adaptation at Run-time. - Jorgen Peddersen; Sri Parameswaran (J. Comput., 2008)

HitME: low power Hit MEmory buffer for embedded systems. - Andhi Janapsatya; Sri Parameswaran; Aleksandar Ignjatovic (ASP-DAC, 2009)

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. - Mohammad Shihabul Haque; Andhi Janapsatya; Sri Parameswaran (CODES+ISSS, 2009)

LOP: a novel SRAM-based architecture for low power and high throughput packet classification. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (CODES+ISSS, 2009)

A design flow for application specific heterogeneous pipelined multiprocessor systems. - Haris Javaid; Sri Parameswaran (DAC, 2009)

CUFFS: An instruction count based architectural framework for security of MPSoCs. - Krutartha Patel; Sri Parameswaran; Roshan G. Ragel (DATE, 2009)

Flexible multi-mode embedded floating-point unit for field programmable gate arrays. - Yee Jern Chong; Sri Parameswaran (FPGA, 2009)

LOP_RE: Range encoding for low power packet classification. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (LCN, 2009)

Security and Dependability of Embedded Systems: A Computer Architects' Perspective. - Jörg Henkel; Vijaykrishnan Narayanan; Sri Parameswaran; Roshan G. Ragel (VLSI Design, 2009)

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (IET Comput. Digit. Tech., 2009)

Custom Floating-Point Unit Generation for Embedded Systems. - Yee Jern Chong; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. - Karin Avnit; Vijay D'Silva; Arcot Sowmya; S. Ramesh; Sri Parameswaran (ACM Trans. Design Autom. Electr. Syst., 2009)

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. - Haris Javaid; Xin He 002; Aleksandar Ignjatovic; Sri Parameswaran (CODES+ISSS, 2010)

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DAC, 2010)

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DATE, 2010)

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. - Andhi Janapsatya; Aleksandar Ignjatovic; Jorgen Peddersen; Sri Parameswaran (DATE, 2010)

Rapid runtime estimation methods for pipelined MPSoCs. - Haris Javaid; Andhi Janapsatya; Mohammad Shihabul Haque; Sri Parameswaran (DATE, 2010)

Optimal WCET-aware code selection for scratchpad memory. - Hui Wu 001; Jingling Xue; Sridevan Parameswaran (EMSOFT, 2010)

Fidelity metrics for estimation models. - Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (ICCAD, 2010)

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. - Roshan G. Ragel; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (DIPES/BICC, 2010)

Improved Architectures for Range Encoding in Packet Classification System. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (NCA, 2010)

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (Des. Autom. Embed. Syst., 2010)

CASES 2009 guest editor's introduction. - Jörg Henkel; Sri Parameswaran (Des. Autom. Embed. Syst., 2010)

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. - Hui Guo 001; Sri Parameswaran (J. Syst. Archit., 2010)

Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. - Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. - Haris Javaid; Muhammad Shafique 001; Sri Parameswaran; Jörg Henkel (DAC, 2011)

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. - Hong Chinh Doan; Haris Javaid; Sri Parameswaran (ESTIMedia, 2011)

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. - Mohammad Shihabul Haque; Jorgen Peddersen; Sri Parameswaran (ICCAD, 2011)

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. - Haris Javaid; Muhammad Shafique 001; Jörg Henkel; Sri Parameswaran (ICCAD, 2011)

A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks. - Ankita Arora; Sri Parameswaran; Roshan G. Ragel; Darshana Jayasinghe (TrustCom, 2011)

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. - Su Myat Min; Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2011)

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran; Aleksandar Ignjatovic (IET Comput. Digit. Tech., 2011)

A hybrid hardware-software technique to improve reliability in embedded processors. - Roshan G. Ragel; Sri Parameswaran (ACM Trans. Embed. Comput. Syst., 2011)

Configurable Multimode Embedded Floating-Point Units for FPGAs. - Yee Jern Chong; Sri Parameswaran (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Architectural Frameworks for Security and Reliability of MPSoCs. - Krutartha Patel; Sri Parameswaran; Roshan G. Ragel (IEEE Trans. Very Large Scale Integr. Syst., 2011)

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. - Mohammad Shihabul Haque; Roshan G. Ragel; Jude Angelo Ambrose; Swarnalatha Radhakrishnan; Sri Parameswaran (CODES+ISSS, 2012)

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. - Tuo Li 001; Roshan G. Ragel; Sri Parameswaran (DATE, 2012)

Fine-grained hardware/software methodology for process migration in MPSoCs. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (ICCAD, 2012)

CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. - Jude Angelo Ambrose; Aleksandar Ignjatovic; Sri Parameswaran (ISCAS, 2012)

A Rapid Methodology for Multi-mode Communication Circuit Generation. - Liang Tang; Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2012)

Randomized Instruction Injection to Counter Power Analysis Attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (ACM Trans. Embed. Comput. Syst., 2012)

Multi-mode pipelined MPSoCs for streaming applications. - Haris Javaid; Daniel Witono; Sri Parameswaran (ASP-DAC, 2013)

RExCache: Rapid exploration of unified last-level cache. - Su Myat Min; Haris Javaid; Sri Parameswaran (ASP-DAC, 2013)

Run-time adaption for highly-complex multi-core systems. - Jörg Henkel; Vijaykrishnan Narayanan; Sri Parameswaran; Jürgen Teich (CODES+ISSS, 2013)

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Semeen Rehman; Jörg Henkel; Sri Parameswaran (DAC, 2013)

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. - Su Myat Min; Haris Javaid; Sri Parameswaran (DAC, 2013)

Reconfigurable pipelined coprocessor for multi-mode communication transmission. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (DAC, 2013)

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Swarnalatha Radhakrishnan; Roshan G. Ragel; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (DATE, 2013)

An extremely compact JPEG encoder for adaptive embedded systems. - Josef Schneider; Sri Parameswaran (DATE, 2013)

System-level optimization of on-chip communication using express links for throughput constrained MPSoCs. - Haseeb Bokhari; Haris Javaid; Sri Parameswaran (ESTIMedia, 2013)

Analyzing the thermal hotspots in FPGA-based embedded systems. - Hussam Amrouch; Thomas Ebi; Josef Schneider; Sridevan Parameswaran; Jörg Henkel (FPL, 2013)

A novel intermittent fault Markov model for deep sub-micron processors. - Babak Saghaie; Roshan G. Ragel; Sri Parameswaran; Aleksandar Ignjatovic (ACM Great Lakes Symposium on VLSI, 2013)

DRMA: dynamically reconfigurable MPSoC architecture. - Lawrance Zhang; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Roshan G. Ragel; Swarnalatha Radhakrishnan; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2013)

Previous messages provide the key to achieve shannon capacity in a wiretap channel. - Shahid Mehraj Shah; Sridevan Parameswaran; Vinod Sharma (ICC Workshops, 2013)

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (ICCAD, 2013)

Energy-aware synthesis of application specific MPSoCs. - Thannirmalai Somu Muthukaruppan; Haris Javaid; Tulika Mitra; Sri Parameswaran (ICCD, 2013)

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. - Jude Angelo Ambrose; Isuru Nawinne; Sri Parameswaran (ISCAS, 2013)

Variable increment step based reconfigurable interleaver for multimode communication application. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (ISCAS, 2013)

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. - Ankita Arora; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (ISVLSI, 2013)

Dynamic encryption key design and management for memory data encryption in embedded systems. - Mei Hong; Hui Guo 001; Sri Parameswaran (ISVLSI, 2013)

A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. - Su Myat Min; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (MECO, 2013)

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. - Roshan G. Ragel; Swarnalatha Radhakrishnan; Jude Angelo Ambrose; Sri Parameswaran (VLSI Design, 2013)

MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (VLSI Design, 2013)

Pipelined Multiprocessor System-on-Chip for Multimedia. - Haris Javaid; Sri Parameswaran (Springer, 2014)

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. - Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Alvin Labios; Yusuke Yachide (ASP-DAC, 2014)

A scorchingly fast FPGA-based Precise L1 LRU cache simulator. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2014)

Dark silicon as a challenge for hardware/software co-design. - Muhammad Shafique 001; Siddharth Garg; Tulika Mitra; Sri Parameswaran; Jörg Henkel (CODES+ISSS, 2014)

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. - Haseeb Bokhari; Haris Javaid; Muhammad Shafique 001; Jörg Henkel; Sri Parameswaran (DAC, 2014)

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. - Haris Javaid; Yusuke Yachide; Su Myat Min Shwe; Haseeb Bokhari; Sri Parameswaran (DAC, 2014)

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (DAC, 2014)

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. - Hong Chinh Doan; Haris Javaid; Sri Parameswaran (DATE, 2014)

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. - Isuru Nawinne; Josef Schneider; Haris Javaid; Sri Parameswaran (DATE, 2014)

Mapping programs for execution on pipelined MPSoCs. - Sri Parameswaran (ESTIMedia, 2014)

Advanced modes in AES: Are they safe from power analysis based side channel attacks? - Darshana Jayasinghe; Roshan G. Ragel; Jude Angelo Ambrose; Aleksandar Ignjatovic; Sri Parameswaran (ICCD, 2014)

A simple digital architecture for a harmonic-cancelling sine-wave synthesizer. - Pasindu Aluthwala; Neil Weste; Andrew Adams; Torsten Lehmann; Sri Parameswaran (ISCAS, 2014)

Reconfigurable Convolutional Codec for Physical Layer Communication Security Application. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran; Sha Zhu (MILCOM, 2014)

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. - Haris Javaid; Muhammad Shafique 001; Jörg Henkel; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs). - Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (IEEE Trans. Parallel Distributed Syst., 2014)

Speeding up single pass simulation of PLRUt caches. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2015)

ADAPT: An adaptive manycore methodology for software pipelined applications. - Xi Zhang 003; Haris Javaid; Muhammad Shafique 001; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (ASP-DAC, 2015)

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (CASES, 2015)

SuperNet: multimode interconnect architecture for manycore chips. - Haseeb Bokhari; Haris Javaid; Muhammad Shafique 001; Jörg Henkel; Sri Parameswaran (DAC, 2015)

Malleable NoC: dark silicon inspired adaptable Network-on-Chip. - Haseeb Bokhari; Haris Javaid; Muhammad Shafique 001; Jörg Henkel; Sri Parameswaran (DATE, 2015)

Dynamic reconfigurable puncturing for secure wireless communication. - Liang Tang; Jude Angelo Ambrose; Akash Kumar 001; Sri Parameswaran (DATE, 2015)

E-pipeline: elastic hardware/software pipelines on a many-core fabric. - Xi Zhang 003; Haris Javaid; Muhammad Shafique 001; Jorgen Peddersen; Jörg Henkel; Sri Parameswaran (DATE, 2015)

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. - Jude Angelo Ambrose; Yusuke Yachide; Kapil Batra; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. - Su Myat Min Shwe; Kapil Batra; Yusuke Yachide; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)

Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power. - Pasindu Aluthwala; Neil Weste; Andrew Adams; Torsten Lehmann; Sri Parameswaran (ISCAS, 2015)

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. - Jude Angelo Ambrose; Nick Higgins; Mrinal Chakravarthy; Shivam Gargg; Tuo Li 001; Daniel Murphy; Aleksandar Ignjatovic; Sri Parameswaran (ISCAS, 2015)

Side channel attacks in embedded systems: A tale of hostilities and deterrence. - Jude Angelo Ambrose; Roshan G. Ragel; Darshana Jayasinghe; Tuo Li 001; Sri Parameswaran (ISQED, 2015)

Dark Silicon: From Computation to Communication. - Jörg Henkel; Haseeb Bokhari; Siddharth Garg; Muhammad Usman Karim Khan; Heba Khdr; Florian Kriebel; Ümit Y. Ogras; Sri Parameswaran; Muhammad Shafique 001 (NOCS, 2015)

ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. - Jude Angelo Ambrose; Tuo Li 001; Daniel Murphy; Shivam Gargg; Nick Higgins; Sri Parameswaran (VLSID, 2015)

SecureD: A Secure Dual Core Embedded Processor. - Roshan G. Ragel; Jude Angelo Ambrose; Sri Parameswaran (CoRR, 2015)

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. - Isuru Nawinne; Haris Javaid; Roshan G. Ragel; Swarnalatha Radhakrishnan; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Improving tag generation for memory data authentication in embedded processor systems. - Tao Liu; Hui Guo 001; Sri Parameswaran; Xiaobo Sharon Hu (ASP-DAC, 2016)

Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure. - Darshana Jayasinghe; Shivam Bhasin; Sri Parameswaran; Aleksandar Ignjatovic (Conf. Computing Frontiers, 2016)

RECORD: Reducing register traffic for checkpointing in embedded processors. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (DATE, 2016)

The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis. - Pasindu Aluthwala; Neil Weste; Andrew Adams; Torsten Lehmann; Sri Parameswaran (ISCAS, 2016)

Self-timed automatic test pattern generation for null convention logic. - Nastaran Nemati; Mark C. Reed; Sri Parameswaran; Karl M. Fant (MWSCAS, 2016)

Processor Design for Soft Errors: Challenges and State of the Art. - Tuo Li 001; Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (ACM Comput. Surv., 2016)

Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052). - Hans Michael Gerndt; Michael Glaß; Sri Parameswaran; Barry L. Rountree (Dagstuhl Reports, 2016)

Editorial Introduction of New Editor-in-Chief and Associate Editors. - Sri Parameswaran (IEEE Embed. Syst. Lett., 2016)

Switchable cache: utilising dark silicon for application specific cache optimisations. - Isuru Nawinne; Haris Javaid; Roshan G. Ragel; Sri Parameswaran (IET Comput. Digit. Tech., 2016)

DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks. - Amin Malekpour; Roshan G. Ragel; Aleksandar Ignjatovic; Sri Parameswaran (ASAP, 2017)

Hardware approximate computing: how, why, when and where? (special session). - Hassaan Saadat; Sri Parameswaran (CASES, 2017)

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs. - Amin Malekpour; Roshan G. Ragel; Aleksandar Ignjatovic; Sri Parameswaran (DAC, 2017)

Social Presence in Social Media: Persuasion, Design and Discourse. - Sri Parameswaran (SIGMIS-CPR, 2017)

NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Sri Parameswaran (VLSID, 2017)

Improved VCF normalization for accurate VCF comparison. - Arash Bayat; Bruno Gaëta; Aleksandar Ignjatovic; Sri Parameswaran (Bioinform., 2017)

iCETD: An improved tag generation design for memory data authentication in embedded processor systems. - Tao Liu; Hui Guo 001; Sri Parameswaran; Xiaobo Sharon Hu (Integr., 2017)

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (IEEE Trans. Computers, 2017)

Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis. - Pasindu Aluthwala; Neil Weste; Andrew Adams; Torsten Lehmann; Sri Parameswaran (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Network-on-Chip Design. - Haseeb Bokhari; Sri Parameswaran (Handbook of Hardware/Software Codesign, 2017)

MESGA: An MPSoC based embedded system solution for short read genome alignment. - Vikkitharan Gnanasambandapillai; Arash Bayat; Sri Parameswaran (ASP-DAC, 2018)

CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support. - Florencia Irena; Daniel Murphy; Sri Parameswaran (ASP-DAC, 2018)

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. - Mubashir Hussain; Amin Malekpour; Hui Guo 001; Sri Parameswaran (ISVLSI, 2018)

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). - Sri Parameswaran; R. Iris Bahar; David Z. Pan (IEEE Des. Test, 2018)

Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication. - Hassaan Saadat; Haseeb Bokhari; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Sri Parameswaran (DAC, 2019)

Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. - Hassaan Saadat; Haris Javaid; Sri Parameswaran (DAC, 2019)

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing. - Amin Malekpour; Roshan G. Ragel; Daniel Murphy; Aleksandar Ignjatovic; Sri Parameswaran (DDECS, 2019)

SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Sri Parameswaran (ICCAD, 2019)

Pairwise alignment of nucleotide sequences using maximal exact matches. - Arash Bayat; Bruno Gaëta; Aleksandar Ignjatovic; Sri Parameswaran (BMC Bioinform., 2019)

SWARAM: Portable Energy and Cost Efficient Embedded System for Genomic Processing. - Ram Prasad Mohanty; Hasindu Gamaarachchi; Andrew J. Lambert; Sri Parameswaran (ACM Trans. Embed. Comput. Syst., 2019)

WEID: Worst-case Error Improvement in Approximate Dividers. - Hassaan Saadat; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (ASP-DAC, 2020)

REALM: Reduced-Error Approximate Log-based Integer Multiplier. - Hassaan Saadat; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (DATE, 2020)

LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. - Farah Abid; Darshana Jayasinghe; Sompasong Somsavaddy; Sri Parameswaran (FPL, 2020)

Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping. - Ann Franchesca Laguna; Hasindu Gamaarachchi; Xunzhao Yin; Michael T. Niemier; Sri Parameswaran; Xiaobo Sharon Hu (ICCAD, 2020)

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. - Hassaan Saadat; Tuo Li 001; Haris Javaid; Sri Parameswaran (VLSID, 2020)

GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis. - Hasindu Gamaarachchi; Wai Chun Lam; Gihan Jayatilaka; Hiruna Samarakoon; Jared T. Simpson; Martin A. Smith; Sri Parameswaran (BMC Bioinform., 2020)

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. - Tuo Li 001; Bradley Hopkins; Sri Parameswaran (CoRR, 2020)

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. - Vikkitharan Gnanasambandapillai; Jorgen Peddersen; Roshan G. Ragel; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach. - Arash Bayat; Nandan P. Deshpande; Marc R. Wilkins; Sri Parameswaran (IEEE ACM Trans. Comput. Biol. Bioinform., 2020)

Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling. - Hasindu Gamaarachchi; Arash Bayat; Bruno Gaëta; Sri Parameswaran (IEEE ACM Trans. Comput. Biol. Bioinform., 2020)

Hardware Trojan Mitigation in Pipelined MPSoCs. - Amin Malekpour; Roshan G. Ragel; Tuo Li 001; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (ACM Trans. Design Autom. Electr. Syst., 2020)

Approximate Computing for ML: State-of-the-art, Challenges and Visions. - Georgios Zervakis 001; Hassaan Saadat; Hussam Amrouch; Andreas Gerstlauer; Sri Parameswaran; Jörg Henkel (ASP-DAC, 2021)

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. - Hsu-Kang Dow; Tuo Li 001; William Miles; Sri Parameswaran (DAC, 2021)

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Sri Parameswaran (IEEE Access, 2021)

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Roshan G. Ragel; Jude Angelo Ambrose; Sri Parameswaran (ACM Trans. Design Autom. Electr. Syst., 2021)

COPS: A complete oblivious processing system. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Hassaan Saadat; Sri Parameswaran (Microprocess. Microsystems, 2021)

FaSe: fast selective flushing to mitigate contention-based cache timing attacks. - Tuo Li 001; Sri Parameswaran (DAC, 2022)

HWST128: complete memory safety accelerator on RISC-V with metadata compression. - Hsu-Kang Dow; Tuo Li 001; Sri Parameswaran (DAC, 2022)

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. - Tuo Li 001; Sri Parameswaran (CoRR, 2022)

Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices. - Po Jui Shih; Hassaan Saadat; Sri Parameswaran; Hasindu Gamaarachchi (CoRR, 2022)

VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs. - Brian Udugama; Darshana Jayasinghe; Hassaan Saadat; Aleksandar Ignjatovic; Sri Parameswaran (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks. - Brian Udugama; Darshana Jayasinghe; Hassaan Saadat; Aleksandar Ignjatovic; Sri Parameswaran (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers. - Darshana Jayasinghe; Brian Udugama; Sri Parameswaran (ASP-DAC, 2023)

Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis. - Hasindu Gamaarachchi; Kisaru Liyanage; Sri Parameswaran (DAC, 2023)

Special Issue: "Approximation at the Edge". - Alberto Bosio; Lara Dolecek; Alexandra Kourfali; Sri Parameswaran; Alessandro Savino (ACM Trans. Embed. Comput. Syst., 2023)

Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis. - Kisaru Liyanage; Hasindu Gamaarachchi; Roshan G. Ragel; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. - Jing Gong; Hassaan Saadat; Hasindu Gamaarachchi; Haris Javaid; Xiaobo Sharon Hu; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Sensors for Remote Power Attacks: New Developments and Challenges. - Brian Udugama; Darshana Jayasinghe; Sri Parameswaran (ASPDAC, 2024)

SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. - Jing Gong; Hassaan Saadat; Haris Javaid; Hasindu Gamaarachchi; David Taubman; Sri Parameswaran (DATE, 2024)

Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. - Kisaru Liyanage; Hasindu Gamaarachchi; Hassaan Saadat; Tuo Li 001; Hiruna Samarakoon; Sri Parameswaran (DATE, 2024)

Optimizing LU Decomposition with RISC-V Based Hardware Acceleration. - Mekala Bindu Bhargavi; Grandhala Sri Sai Harshith; Sri Parameswaran; Soumya J. (ISVLSI, 2024)

Optimizing Convolutional Image Processing on RISC-V Using Branch Prediction on FPGA. - Mekala Bindu Bhargavi; Sujay Krishnan Subramanian; Sri Parameswaran; Soumya J. (TENCON, 2024)

Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. - Mekala Bindu Bhargavi; Sai Siddharth Rokkam; Sri Parameswaran; Soumya J. (VDAT, 2024)

Physical and Software Based Fault Injection Attacks Against TEEs in Mobile Devices: A Systemisation of Knowledge. - Aaron Joy; Ben Soh; Zhi Zhang; Sri Parameswaran; Darshana Jayasinghe (CoRR, 2024)

1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables. - Darshana Jayasinghe; Brian Udugama; Sri Parameswaran (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Sri Parameswaran (IEEE Trans. Dependable Secur. Comput., 2024)