New highly-accurate CMOS source-degenerated based V-I converter with positive feedback. - Jaime Ramírez-Angulo; Belén Calvo; Sri Raga Sudha Garimella; Santiago Celma; Maria Teresa Sanz (ECCTD, 2007)

Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor. - Sri Raga Sudha Garimella; Jaime Ramírez-Angulo; Antonio J. López-Martín; Ramón González Carvajal (ISCAS, 2008)

Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters. - Sri Raga Sudha Garimella (VLSI Design, 2008)

An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. - Jaime Ramírez-Angulo; Lalitha Mohana Kalyani-Garimella; Annajirao Garimella; Sri Raga Sudha Garimella; Antonio J. López-Martín; Ramón González Carvajal (VLSI Design, 2008)

New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A. - Lalitha Mohana Kalyani-Garimella; Sri Raga Sudha Garimella; Kevin Duda; Eric S. Fetzer (MWSCAS, 2013)

Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow. - Lalitha Mohana Kalyani-Garimella; Sri Raga Sudha Garimella (MWSCAS, 2019)