Test pattern generation for timing-induced functional errors in hardware-software systems. - Srikanth Arekapudi; Fei Xin; Jinzheng Peng; Ian G. Harris (HLDVT, 2001)

ATPG for timing-induced functional errors on trigger events in hardware-software systems. - Srikanth Arekapudi; Fei Xin; Jinzheng Peng; Ian G. Harris (ETW, 2002)

ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. - Srikanth Arekapudi; Fei Xin; Jinzheng Peng; Ian G. Harris (J. Circuits Syst. Comput., 2003)

Configuring a load-balanced switch in hardware. - Srikanth Arekapudi; Shang-Tse Chuang; Isaac Keslassy; Nick McKeown (Hot Interconnects, 2004)

A low-power distributed wide-band LNA in 0.18µm CMOS. - Srikanth Arekapudi; Echere Iroaga; Boris Murmann (ISCAS (5), 2005)

Using Hardware to Configure a Load-Balanced Switch. - Srikanth Arekapudi; Shang-Tse Chuang; Isaac Keslassy; Nick McKeown (IEEE Micro, 2005)

A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support. - Michael Golden; Srikanth Arekapudi; Greg Dabney; Mike Haertel; Stephen Hale; Lowell Herlinger; Yongg Kim; Kevin McGrath; Vasant Palisetti; Monica Singh (ISSCC, 2006)

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. - Tim C. Fischer; Srikanth Arekapudi; Eric Busta; Carl Dietz; Michael Golden; Scott Hilker; Aaron Horiuchi; Kevin A. Hurd; Dave Johnson 002; Hugh McIntyre; Samuel Naffziger; James Vinh; et al. (ISSCC, 2011)

40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. - Michael Golden; Srikanth Arekapudi; James Vinh (ISSCC, 2011)

Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. - Hugh McIntyre; Srikanth Arekapudi; Eric Busta; Timothy C. Fischer; Michael Golden; Aaron Horiuchi; Tom Meneghini; Samuel Naffziger; James Vinh (IEEE J. Solid State Circuits, 2012)

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. - Visvesh S. Sathe 001; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger (IEEE J. Solid State Circuits, 2013)

Carrizo: A High Performance, Energy Efficient 28 nm APU. - Benjamin Munger; David Akeson; Srikanth Arekapudi; Tom Burd; Harry R. Fair III; Jim Farrell; Dave Johnson 002; Guhan Krishnan; Hugh McIntyre; Edward McLellan; Samuel Naffziger; Russell Schreiber; et al. (IEEE J. Solid State Circuits, 2016)