Hirecs: Hypercube Implementation of Relaxation-Based Circuit Simulation. - Srilata Raman; Lalit M. Patnaik (Int. J. High Speed Comput., 1989)

An Annealing-Based Circuit Partitioner for Hypercube Architecture: Design and Performance Evaluation. - Srilata Raman; Lalit M. Patnaik (Int. J. High Speed Comput., 1990)

Parallel Implementation of Circuit Simulation. - Srilata Raman; Lalit M. Patnaik; Rajib Mall (Int. J. High Speed Comput., 1990)

Quality-time tradeoffs in simulated annealing for VLSI placement. - Srilata Raman; Benjamin W. Wah (COMPSAC, 1991)

A delay driven FPGA placement algorithm. - Srilata Raman; C. L. Liu 001; Larry G. Jones (EURO-DAC, 1994)

A Parallel Simulated Annealing-Based Channel Router. - Rajib Mall; Srilata Raman; Lalit M. Patnaik (Int. J. High Speed Comput., 1994)

A genetic algorithm-based circuit partitioner for MCMs. - Ananta K. Majhi; Lalit M. Patnaik; Srilata Raman (Microprocess. Microprogramming, 1995)

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. - Srilata Raman; C. L. Liu 001; Larry G. Jones (ED&TC, 1996)

Performance-driven MCM partitioning through an adaptive genetic algorithm. - Srilata Raman; Lalit M. Patnaik (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. - Srilata Raman; C. L. Liu 001; Larry G. Jones (VLSI Design, 1996)

CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. - Mohankumar Guruswamy; Robert L. Maziasz; Daniel Dulitz; Srilata Raman; Venkat Chiluvuri; Andrea Fernandez; Larry G. Jones (DAC, 1997)

Optimization Via Evolutionary Processes. - Srilata Raman; Lalit M. Patnaik (Adv. Comput., 1997)