Minimizing stand-by leakage power in static CMOS circuits. - Srinath R. Naidu; E. T. A. F. Jacobs (DATE, 2001)

Timing Yield Calculation Using an Impulse-Train Approach. - Srinath R. Naidu (ASP-DAC/VLSI Design, 2002)

On Synthesis of Easily Testable (k, K) Circuits. - Srinath R. Naidu; Vijay Chandru (IEEE Trans. Computers, 2003)

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. - Jochen A. G. Jess; Kerim Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Use of statistical timing analysis on real designs. - A. Nardi; Emre Tuncer; Srinath R. Naidu; A. Antonau; S. Gradinaru; Tao Lin; J. Song (DATE, 2007)

Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. - Srinath R. Naidu (VLSI Design, 2007)

Geometric Programming Formulation for Gate Sizing with Pipelining Constraints. - Srinath R. Naidu (VLSID, 2015)

Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization. - Sita Kondamadugula; Srinath R. Naidu (ACM Great Lakes Symposium on VLSI, 2016)

Accelerated evolutionary algorithms with parameterimportance based population initialization for variation-aware analog yield optimization. - Sita Kondamadugula; Srinath R. Naidu (MWSCAS, 2016)

Fast Approach for Iris Detection on GPU by Applying Search Localization for Circular Hough Transform. - Pinkey Kumari; Srinath R. Naidu (ICACCI, 2018)

Optimal oversampling ratio in two-step simulation. - Srinath R. Naidu; Gopalakrishnan Venkiteswaran (Monte Carlo Methods Appl., 2024)