Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. - Srinivas Boppu; Frank Hannig; Jürgen Teich; Roberto Perez-Andrade (ReConFig, 2011)

Design of Low Power On-chip Processor Arrays. - Vahid Lari; Shravan Muddasani; Srinivas Boppu; Frank Hannig; Jürgen Teich (ASAP, 2012)

A prototype of an invasive tightly-coupled processor array. - Shravan Muddasani; Srinivas Boppu; Frank Hannig; Boris Kuzmin; Vahid Lari; Jürgen Teich (DASIP, 2012)

Hierarchical power management for adaptive tightly-coupled processor arrays. - Vahid Lari; Shravan Muddasani; Srinivas Boppu; Frank Hannig; Moritz Schmid; Jürgen Teich (ACM Trans. Design Autom. Electr. Syst., 2012)

Loop program mapping and compact code generation for programmable hardware accelerators. - Srinivas Boppu; Frank Hannig; Jürgen Teich (ASAP, 2013)

System integration of tightly-coupled processor arrays using reconfigurable buffer structures. - Frank Hannig; Moritz Schmid; Vahid Lari; Srinivas Boppu; Jürgen Teich (Conf. Computing Frontiers, 2013)

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. - Frank Hannig; Vahid Lari; Srinivas Boppu; Alexandru Tanase; Oliver Reiche (ACM Trans. Embed. Comput. Syst., 2014)

Compact Code Generation for Tightly-Coupled Processor Arrays. - Srinivas Boppu; Frank Hannig; Jürgen Teich (J. Signal Process. Syst., 2014)

Code Generation for Tightly Coupled Processor Arrays. - Srinivas Boppu (2015)

Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization. - Spandan Dey; Srinivas Boppu; M. Sabarimalai Manikandan (ICDIPC, 2019)

An Automated Algorithm for Estimating Respiration Rate from PPG Signals. - Kinjarapu Manojkumar; Srinivas Boppu; M. Sabarimalai Manikandan (MIND (2), 2020)

Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. - Arvind Thumatti K. R.; Marcel Brand; Christian Heidorn; Srinivas Boppu; Frank Hannig; Jürgen Teich (VDAT, 2020)

Design and Implementation of Optimized Register File for Streaming Applications. - Ayazulla Khan Patan; Dimitrios Stathis 001; Pudi Dhilleswararao; Yu Yang; Srinivas Boppu; Ahmed Hemani (VDAT, 2021)

Efficient Multiplication and Accumulation of Signed Numbers. - Susheel Ujwal Siddamshetty; Suresh Nambi; Srinivas Boppu; Debapratim Ghosh (iSES, 2022)

Hand Gesture Recognition System in the Complex Background for Edge Computing Devices. - Chakkapalli Manikanta Suryateja; Srinivas Boppu; Linga Reddy Cenkeramaddi; Barathram Ramkumar (iSES, 2022)

A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization. - Ashish Reddy Bommana; Srinivas Boppu (MCSoC, 2022)

Efficient Hardware Architecture for Posit Addition/Subtraction. - Susheel Ujwal Siddamshetty; Srinivas Boppu; Debapratim Ghosh (MCSoC, 2022)

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey. - Pudi Dhilleswararao; Srinivas Boppu; M. Sabarimalai Manikandan; Linga Reddy Cenkeramaddi (IEEE Access, 2022)

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Vamsi Goudu; Srinivas Boppu; Ahmed Hemani (DSD, 2023)

Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices. - Yalagala Sivanjaneyulu; Srinivas Boppu; M. Sabarimalai Manikandan (ECAI, 2023)

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Srinivas Boppu; Yu Yang; Ahmed Hemani (HEART, 2023)

Implementation of Image Averaging on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Vamsi Goudu; Srinivas Boppu; Ritika Ratnu; Ahmed Hemani (SBCCI, 2023)

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. - Reeshita Kallapu; Dimitrios Stathis 001; Srinivas Boppu; Ahmed Hemani (VLSID, 2023)

Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. - Ashish Reddy Bommana; Susheel Ujwal Siddamshetty; Pudi Dhilleswararao; Arvind Thumatti K. R.; Srinivas Boppu; M. Sabarimalai Manikandan; Linga Reddy Cenkeramaddi (ACM Trans. Design Autom. Electr. Syst., 2023)

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. - Pudi Dhilleswararao; Shivam Malviya; Srinivas Boppu; Yu Yang; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. - Pudi Dhilleswararao; Yu Yang; Dimitrios Stathis 001; Sunil Kumar Prajapati; Srinivas Boppu; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Resource-Efficient Derivative PPG-Based Signal Quality Assessment Using One-Dimensional CNN With Optimal Hyperparameters for Quality-Aware PPG Analysis. - Yalagala Sivanjaneyulu; M. Sabarimalai Manikandan; Srinivas Boppu; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Automating functional unit and register binding for synchoros CGRA platform. - Pudi Dhilleswararao; Utsav Tiwari; Srinivas Boppu; Yu Yang; Ahmed Hemani (Des. Autom. Embed. Syst., 2024)

In-Memory Computing Architecture for Tsetlin Machine Inference using MTJ-based Crossbar. - Akash Kumar; Vineeth Botsa; Omar Ghazal; Srinivas Boppu; Rishad Shafik (ISCAS, 2025)

Quality-Aware PPG-Based Blood Pressure Classification for Energy-Efficient Trustworthy BP Monitoring Devices With Reduced False Alarms. - Yalagala Sivanjaneyulu; M. Sabarimalai Manikandan; Srinivas Boppu; Linga Reddy Cenkeramaddi (IEEE Access, 2025)