A test generation system for path delay faults. - Srinivas Patil; Sudhakar M. Reddy (ICCD, 1989)

Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. - Srinivas Patil; Prithviraj Banerjee (ITC, 1989)

Efficient circuit partitioning algorithms for parallel logic simulation. - Srinivas Patil; Prithviraj Banerjee; Constantine D. Polychronopoulos (SC, 1989)

A parallel branch and bound algorithm for test generation. - Srinivas Patil; Prithviraj Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. - Srinivas Patil; Prithviraj Banerjee; Janak H. Patel (DAC, 1991)

A Layout Driven Design for Testability Technique for MOS VLSI Circuits. - Sungho Kim; Prithviraj Banerjee; Srinivas Patil (ITC, 1991)

Performance trade-offs in a parallel test generation/fault simulation environment. - Srinivas Patil; Prithviraj Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Parallel algorithms for test generation and fault simulation - Srinivas Patil (1991)

Skewed-Load Transition Test: Part 2, Coverage. - Srinivas Patil; Jacob Savir (ITC, 1992)

Scan-based transition test. - Jacob Savir; Srinivas Patil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design of an Efficient Weighted-Random-Pattern Generation System. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (ITC, 1994)

On broad-side delay test. - Jacob Savir; Srinivas Patil (IEEE Trans. Very Large Scale Integr. Syst., 1994)

A weighted random pattern test generation system. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Compressing Functional Tests for Microprocessors. - Kedarnath J. Balakrishnan; Nur A. Touba; Srinivas Patil (Asian Test Symposium, 2005)

A Functional Fault Model with Implicit Fault Effect Propagation Requirements. - Irith Pomeranz; Srinivas Patil; Praveen Parvathala (ATS, 2006)

Selecting High-Quality Delay Tests for Manufacturing Test and Debug. - Hangkyu Lee; Suriyaprakash Natarajan; Srinivas Patil; Irith Pomeranz (DFT, 2006)

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. - Sungchul Park; Li Chen; Praveen Parvathala; Srinivas Patil; Irith Pomeranz (ITC, 2006)

Path Delay Fault Simulation on Large Industrial Designs. - Suriyaprakash Natarajan; Srinivas Patil; Sreejit Chakravarty (VTS, 2006)

The Region-Exhaustive Fault Model. - Abhijit Jas; Suriyaprakash Natarajan; Srinivas Patil (ATS, 2007)

Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. - Irith Pomeranz; Praveen Parvathala; Srinivas Patil (ATS, 2007)

Analysis of Specified Bit Handling Capability of Combinational Expander Networks. - Abhijit Jas; Srinivas Patil (DFT, 2007)

A low-cost concurrent error detection technique for processor control logic. - Ramtilak Vemu; Abhijit Jas; Jacob A. Abraham; Srinivas Patil; Rajesh Galivanche (DATE, 2008)

RT-Level Deviation-Based Grading of Functional Test Sequences. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (VTS, 2009)

The Challenges of Nanotechnology and Gigacomplexity. - Gadi Singer; Rajesh Galivanche; Srinivas Patil; Mike Tripp (IEEE Des. Test Comput., 2009)

FPGA-based hardware acceleration for Boolean satisfiability. - Kanupriya Gulati; Suganth Paul; Sunil P. Khatri; Srinivas Patil; Abhijit Jas (ACM Trans. Design Autom. Electr. Syst., 2009)

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. - Naghmeh Karimi; Zhiqiu Kong; Krishnendu Chakrabarty; Pallav Gupta; Srinivas Patil (Asian Test Symposium, 2011)

Test generation for clock-domain crossing faults in integrated circuits. - Naghmeh Karimi; Krishnendu Chakrabarty; Pallav Gupta; Srinivas Patil (DATE, 2012)

Functional Test-Sequence Grading at Register-Transfer Level. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (IEEE Trans. Very Large Scale Integr. Syst., 2012)