A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). - David Jefferson; Srinivas Reddy; Christopher Lane; Ninh Ngo; Wanli Chang 003; Manuel Mijia; Ketan Zaveri; Cameron McClintock; Richard Cliff (FPGA, 1998)

A next generation architecture optimized for high density system level integration. - Richard Cliff; Srinivas Reddy; Cameron McClintock; David Jefferslon; Christopher Lane; Ketan Zaveri; Manuel Mejia; Andy Lee; Ninh Ngo; Risa Altaf; Bruce Pedersen; Frank Heile; et al. (CICC, 1999)

The StratixTM routing and logic architecture. - David M. Lewis; Vaughn Betz; David Jefferson; Andy Lee; Christopher Lane; Paul Leventis; Sandy Marquardt; Cameron McClintock; Bruce Pedersen; Giles Powell; Srinivas Reddy; Chris Wysocki; et al. (FPGA, 2003)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

Profile-Based Load Scheduling in Wireless Energy Harvesting Sensors for Data Rate Maximization. - Srinivas Reddy; Chandra R. Murthy (ICC, 2010)

Duty cycling and power management with a network of energy harvesting sensors. - Srinivas Reddy; Chandra R. Murthy (CAMSAP, 2011)

Art for reward's sake: Visual art recruits the ventral striatum. - Simon Lacey; Henrik Hagtvedt; Vanessa M. Patrick; Amy Anderson; Randall Stilla; Gopikrishna Deshpande; Xiaoping Hu 001; João R. Sato; Srinivas Reddy; Krish Sathian (NeuroImage, 2011)

Dual-Stage Power Management Algorithms for Energy Harvesting Sensors. - Srinivas Reddy; Chandra R. Murthy (IEEE Trans. Wirel. Commun., 2012)