A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market. - Basireddy Karunakar Reddy; Srinivas Sabbavarapu; Kshitiz Gupta; Rayapati Prabhat; Amit Acharyya; Rishad A. Shafik; Jimson Mathew (ISED, 2013)

A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept. - Srinivas Sabbavarapu; Basireddy Karunakar Reddy; Rayapati Prabhat; Kshitiz Gupta; Amit Acharyya; Rishad Ahmed Shafik; Jimson Mathew (ISED, 2013)

A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry. - Basireddy Karunakar Reddy; Srinivas Sabbavarapu; Amit Acharyya (ISCAS, 2014)

Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG). - Basireddy Karunakar Reddy; Srinivas Sabbavarapu; Amit Acharyya (ISED, 2014)

A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market. - Srinivas Sabbavarapu; Basireddy Karunakar Reddy; Amit Acharyya (ISED, 2014)

A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market. - Srinivas Sabbavarapu; Basireddy Karunakar Reddy; N. Srinivasulu; Amit Acharyya; Jimson Mathew (J. Low Power Electron., 2014)

Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing. - Srinivas Sabbavarapu; Basireddy Karunakar Reddy; Amit Acharyya; S. Saqib Khursheed (J. Low Power Electron., 2017)

Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction. - Basireddy Karunakar Reddy; Srinivas Sabbavarapu; Amit Acharyya (J. Low Power Electron., 2018)

Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time. - Srinivas Sabbavarapu; Basireddy Karunakar Reddy; Amit Acharyya (J. Low Power Electron., 2018)