Framework for Synthesis of Virtual Pipelines. - Srinivasan Dasasathyan; Rajesh Radhakrishnan; Ranga Vemuri (ASP-DAC/VLSI Design, 2002)

Clock-Aware FPGA Placement Contest. - Stephen Yang; Chandra Mulpuri; Sainath Reddy; Meghraj Kalase; Srinivasan Dasasathyan; Mehrdad E. Dehkordi; Marvin Tom; Rajat Aggarwal (ISPD, 2017)