Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology. - B. Srinivasu 001; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs. - B. Srinivasu 001; K. Sridharan 001 (IET Circuits Devices Syst., 2017)

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies. - B. Srinivasu 001; K. Sridharan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

CoLPUF : A Novel Configurable LFSR-based PUF. - B. Srinivasu 001; Vikramkumar Pudi; Anupam Chattopadhyay; Kwok-Yan Lam (APCCAS, 2018)

High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. - Panasa Srikanth; B. Srinivasu 001 (VDAT, 2022)

Memristor-based High Speed and Area Efficient Comparators in IMPLY Logic. - Nandit Kaushik; B. Srinivasu 001 (VLSID, 2023)

High-Speed Serial and Semi-Parallel IMPLY-based Approximate Adders through Memristors for In-Memory Computing. - Nandit Kaushik; L. Hemanth Krishna; Srinivasu Bodapati 001 (ISCAS, 2024)

Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers. - L. Hemanth Krishna; Nandit Kaushik; Srinivasu Bodapati 001 (ISCAS, 2024)

Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks. - L. Hemanth Krishna; B. Srinivasu 001 (ISVLSI, 2024)

Energy Efficient Memristor-Based Subtractors and Comparator for In-Memory Computing in MAGIC. - Nandit Kaushik; B. Srinivasu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor. - L. Hemanth Krishna; Sreehari Veeramachaneni; Srinivasu Bodapati 001; Bhaskara Rao Jammu 001; Sk. Noor Mahammad (VLSID, 2025)

MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors. - Shri Janani Senthil; B. Srinivasu 001 (VLSID, 2025)

Advancing Neural Network Performance with Probabilistic Computing for ReLU Function. - Amit Singh; Amit Kumar Jangid; B. Srinivasu 001 (VLSID, 2025)

Low Power Approximate Multiplier Architecture for Deep Neural Networks. - Pragun Jaswal; L. Hemanth Krishna; B. Srinivasu 001 (CoRR, 2025)

Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications. - L. Hemanth Krishna; Srinivasu Bodapati 001; Sreehari Veeramachaneni; Bhaskara Rao Jammu 001; Noor Mahammad Sk (CoRR, 2025)

Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic. - L. Hemanth Krishna; B. Srinivasu 001; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

High-Performance Gemmini-Based Matrix Multiplication Accelerator for Deep Learning Workloads. - Anurag Sharma; L. Hemanth Krishna; B. Srinivasu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication. - Pragun Jaswal; L. Hemanth Krishna; B. Srinivasu 001 (VLSID, 2026)

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core. - Pragun Jaswal; L. Hemanth Krishna; B. Srinivasu 001 (CoRR, 2026)