Rapid Prototyping of Reconfigurable Coprocessors. - Naren Narasimhan; Vinoo Srinivasan; Madhavi Vootukuru; Jeffrey Walrath; Sriram Govindarajan; Ranga Vemuri (ASAP, 1996)

Cone-based clustering heuristic for list-scheduling algorithms. - Sriram Govindarajan; Ranga Vemuri (ED&TC, 1997)

Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. - Sriram Govindarajan; Ranga Vemuri (ICCD, 1997)

An Effective Design System for Dynamically Reconfigurable Architectures. - Sriram Govindarajan; Iyad Ouaiss; Meenakshi Kaul; Vinoo Srinivasan; Ranga Vemuri (FCCM, 1998)

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. - Iyad Ouaiss; Sriram Govindarajan; Vinoo Srinivasan; Meenakshi Kaul; Ranga Vemuri (IPPS/SPDP Workshops, 1998)

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. - Meenakshi Kaul; Ranga Vemuri; Sriram Govindarajan; Iyad Ouaiss (DAC, 1999)

Improving the Schedule Quality of Static-List Time-Constrained Scheduling. - Sriram Govindarajan; Ranga Vemuri (DATE, 2000)

Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. - Sriram Govindarajan; Ranga Vemuri (FPL, 2000)

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. - Preetham Lakshmikanthan; Sriram Govindarajan; Vinoo Srinivasan; Ranga Vemuri (IPDPS Workshops, 2000)

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. - Sriram Govindarajan; Vinoo Srinivasan; Preetham Lakshmikanthan; Ranga Vemuri (VLSI Design, 2000)

Application Specific Macro Based Synthesis. - Sujatha Sundararaman; Sriram Govindarajan; Ranga Vemuri (VLSI Design, 2001)

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. - Naren Narasimhan; Elena Teica; Rajesh Radhakrishnan; Sriram Govindarajan; Ranga Vemuri (Formal Methods Syst. Des., 2001)

Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. - V. Srinivasan; Sriram Govindarajan; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2001)