5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. - Sriram R. Vangal; Yatin Vasant Hoskote; Nitin Borkar; Atila Alvandpour (IEEE J. Solid State Circuits, 2006)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Priya Iyer; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Sriram Venkataraman; et al. (ISSCC, 2007)

A 5-GHz Mesh Interconnect for a Teraflops Processor. - Yatin Hoskote; Sriram R. Vangal; Arvind P. Singh; Nitin Borkar; Shekhar Borkar (IEEE Micro, 2007)

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Vasantha Erraguntla; Clark Roberts; et al. (IEEE J. Solid State Circuits, 2008)

On-Chip Networks for Multicore Systems. - Li-Shiuan Peh; Stephen W. Keckler; Sriram R. Vangal (Multicore Processors and Systems, 2009)

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

The 48-core SCC Processor: the Programmer's View. - Timothy G. Mattson; Michael Riepen; Thomas Lehnig; Paul Brett; Werner Haas 002; Patrick Kennedy; Jason Howard; Sriram R. Vangal; Nitin Borkar; Gregory Ruhl; Saurabh Dighe (SC, 2010)

A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. - Shailendra Jain; Vasantha Erraguntla; Sriram R. Vangal; Yatin Vasant Hoskote; Nitin Borkar; Tulasi Mandepudi; V. P. Karthik (VLSI Design, 2010)

Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies. - Partha Pratim Pande; Sriram R. Vangal (IEEE Des. Test Comput., 2010)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. - Praveen Salihundam; Shailendra Jain; Tiju Jacob; Shasi Kumar; Vasantha Erraguntla; Yatin Vasant Hoskote; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar (IEEE J. Solid State Circuits, 2011)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. - Praveen Salihundam; Mohammed Asadullah Khan; Shailendra Jain; Yatin Vasant Hoskote; Satish Yada; Shasi Kumar; Vasantha Erraguntla; Sriram R. Vangal; Nitin Borkar (VLSI Design, 2012)

IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Sriram R. Vangal (IEEE Micro, 2013)

Resiliency for many-core system on a chip. - Tanay Karnik; James W. Tschanz; Nitin Borkar; Jason Howard; Sriram R. Vangal; Vivek De; Shekhar Borkar (ASP-DAC, 2014)

A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor. - Sriram R. Vangal; Shailendra Jain; Vivek De (ICICDT, 2014)

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Sandeep Jain; Sriram R. Vangal; James W. Tschanz; Vivek De (VLSI Circuits, 2016)

Test implications and challenges in near threshold computing special session. - Mehdi Baradaran Tahoori; Rob Aitken; Sriram R. Vangal; Bal Sandhu (VTS, 2016)

Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era. - Vivek De; Sriram R. Vangal; Ram Krishnamurthy 001 (IEEE Des. Test, 2017)

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Tao Wang; Sriram R. Vangal; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2017)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). - Pedram Mohseni; Sriram R. Vangal (IEEE J. Solid State Circuits, 2019)

Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee. - Sriram R. Vangal; Long Yan; Frederic Gianesello (ISSCC, 2021)

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. - Sriram R. Vangal; Somnath Paul; Steven Hsu; Amit Agarwal 001; Saurabh Kumar 003; Ram Krishnamurthy 001; Harish Krishnamurthy; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)