Delay Constrained Register Transfer Level Dynamic Power Estimation. - Sriram Sambamurthy; Jacob A. Abraham; Raghuram S. Tupuri (PATMOS, 2006)

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. - Sriram Sambamurthy; Jacob A. Abraham; Raghuram S. Tupuri (VLSI Design, 2008)

Functionally valid gate-level peak power estimation for processors. - Sriram Sambamurthy; Sankar Gurumurthy; Ramtilak Vemu; Jacob A. Abraham (ISQED, 2009)

Estimation of maximum application-level power supply noise. - Tung-Yeh Wu; Sriram Sambamurthy; Jacob A. Abraham (SoCC, 2010)

Unified Power Frequency Model Framework. - Sriram Sundaram; Warren He; Sriram Sambamurthy; Aaron Grenat; Steven Liepe; Samuel Naffziger (ISLPED, 2016)

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. - Aaron Grenat; Sriram Sundaram; Stephen Kosonocky; Ravinder Rachala; Sriram Sambamurthy; Steven Liepe; Miguel Rodriguez; Tom Burd; Adam Clark; Michael Austin; Samuel Naffziger (ISSCC, 2016)

Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. - Sriram Sundaram; Sriram Sambamurthy; Michael Austin; Aaron Grenat; Michael Golden; Stephen Kosonocky; Samuel Naffziger (VLSID, 2016)

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. - Sriram Sundaram; Aaron Grenat; Samuel Naffziger; Tom Burd; Stephen Kosonocky; Steven Liepe; Ravinder Rachala; Miguel Rodriguez; Michael Austin; Sriram Sambamurthy (IEEE J. Solid State Circuits, 2017)