Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques. - Mudit Bhargava; Y. K. Chong; Vincent Schuppe; Bikas Maiti; Martin Kinkade; Hsin-Yu Chen; Andy W. Chen; Sanjay Mangal; Jacek Wiatrowski; Gerald Gouya; Abhishek Baradia; Sriram Thyagarajan; et al. (VLSIC, 2014)

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. - Cagla Cakir; Andy W. Chen; Y. K. Chong; Sriram Thyagarajan; Mark P. McCartney; Peixuan Tan; Yulin Shi; Mudit Bhargava (VLSI Circuits, 2019)