Energy efficiency limits of logic and memory. - Sapan Agarwal; Jeanine E. Cook; Erik DeBenedictis; Michael P. Frank; Gert Cauwenberghs; Sriseshan Srikanth; Bobin Deng; Eric R. Hein; Paul G. Rabbat; Thomas M. Conte (ICRC, 2016)

Computationally-redundant energy-efficient processing for y'all (CREEPY). - Bobin Deng; Sriseshan Srikanth; Eric R. Hein; Paul G. Rabbat; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (ICRC, 2016)

A Brief Survey of Non-Residue Based Computational Error Correction. - Sriseshan Srikanth; Bobin Deng; Thomas M. Conte (CoRR, 2016)

Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. - Erik P. DeBenedictis; Jeanine E. Cook; Sriseshan Srikanth; Thomas M. Conte (HPEC, 2017)

The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. - Sriseshan Srikanth; Thomas M. Conte; Erik P. DeBenedictis; Jeanine E. Cook (ICRC, 2017)

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. - Sriseshan Srikanth; Paul G. Rabbat; Eric R. Hein; Bobin Deng; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook; Michael P. Frank (HPCA, 2018)

Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip. - Anirudh Jain; Sriseshan Srikanth; Erik P. DeBenedictis; Tushar Krishna (ICRC, 2018)

Tackling memory access latency through DRAM row management. - Sriseshan Srikanth; Lavanya Subramanian; Sreenivas Subramoney; Thomas M. Conte; Hong Wang 003 (MEMSYS, 2018)

Extending Moore's Law via Computationally Error-Tolerant Computing. - Bobin Deng; Sriseshan Srikanth; Eric R. Hein; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook; Michael P. Frank (ACM Trans. Archit. Code Optim., 2018)

Experimental Insights from the Rogues Gallery. - Jeffrey S. Young 001; E. Jason Riedy; Thomas M. Conte; Vivek Sarkar; Prasanth Chatarasi; Sriseshan Srikanth (ICRC, 2019)

Intrepydd: performance, productivity, and portability for data science application kernels. - Tong Zhou 007; Jun Shirako; Anirudh Jain; Sriseshan Srikanth; Thomas M. Conte; Richard W. Vuduc; Vivek Sarkar (Onward!, 2020)

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. - Sriseshan Srikanth; Anirudh Jain; Joseph M. Lennon; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (ACM Trans. Archit. Code Optim., 2020)

Energy efficient architectures for irregular data streams. - Sriseshan Srikanth (2020)

SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. - Sriseshan Srikanth; Anirudh Jain; Thomas M. Conte; Erik P. DeBenedictis; Jeanine E. Cook (ACM Trans. Archit. Code Optim., 2021)

Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. - Bobin Deng; Sriseshan Srikanth; Anirudh Jain; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (IEEE Trans. Computers, 2022)

SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping. - Armand Behroozi; Yuxiang Chen; Vlad Fruchter; Lavanya Subramanian; Sriseshan Srikanth; Scott A. Mahlke (ASPLOS (3), 2024)

Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. - Lita Yang; Changjung Kao; Sriseshan Srikanth; Huseyin Ekin Sumbul; Tony F. Wu; Huichu Liu; Edith Beigné (MEMSYS, 2024)