Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ICCAD, 1998)

TAO: regular expression based high-level testability analysis and optimization. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ITC, 1998)

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. - Srivaths Ravi 001; Indradeep Ghosh; Rabindra K. Roy; Sujit Dey (J. Electron. Test., 1998)

A framework for testing core-based systems-on-a-chip. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ICCAD, 1999)

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (VTS, 1999)

A Technique for Identifying RTL and Gate-Level Correspondences. - Srivaths Ravi 001; Niraj K. Jha; Indradeep Ghosh; Vamsi Boppana (ICCD, 2000)

: Reducing test application time in high-level test generation. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ITC, 2000)

High-Level Synthesis with Variable-Latency Components. - Vijay Raghunathan; Srivaths Ravi 001; Ganesh Lakshminarayana (VLSI Design, 2000)

Integrating variable-latency components into high-level synthesis. - Vijay Raghunathan; Srivaths Ravi 001; Ganesh Lakshminarayana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Transient Power Management Through High Level Synthesis. - Vijay Raghunathan; Srivaths Ravi 001; Anand Raghunathan; Ganesh Lakshminarayana (ICCAD, 2001)

Fast test generation for circuits with RTL and gate-level views. - Srivaths Ravi 001; Niraj K. Jha (ITC, 2001)

Synthesis of System-on-a-chip for Testability. - Srivaths Ravi 001; Niraj K. Jha (VLSI Design, 2001)

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. - Srivaths Ravi 001; Indradeep Ghosh; Vamsi Boppana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Testing of core-based systems-on-a-chip. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

TAO: regular expression-based register-transfer level testability analysis and optimization. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2001)

FLEXBAR: A crossbar switching fabric with improved performance and utilization. - Jacob Chang; Srivaths Ravi 001; Anand Raghunathan (CICC, 2002)

System design methodologies for a wireless security processing platform. - Srivaths Ravi 001; Anand Raghunathan; Nachiketh R. Potlapally; Murugan Sankaradass (DAC, 2002)

Optimizing public-key encryption for wireless clients. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Ganesh Lakshminarayana (ICC, 2002)

High-level synthesis of distributed logic-memory architectures. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2002)

Synthesis of custom processors based on extensible platforms. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2002)

Securing Wireless Data: System Architecture Challenges. - Anand Raghunathan; Nachiketh R. Potlapally; Srivaths Ravi 001 (ISSS, 2002)

Special Session: Security on SoC. - Hiroto Yasuura; Naofumi Takagi; Srivaths Ravi 001; Michael Torla; Catherine H. Gebotys (ISSS, 2002)

Test synthesis of systems-on-a-chip. - Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

High-level test compaction techniques. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A scalable software-based self-test methodology for programmable processors. - Li Chen; Srivaths Ravi 001; Anand Raghunathan; Sujit Dey (DAC, 2003)

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. - Davide Bertozzi; Anand Raghunathan; Luca Benini; Srivaths Ravi 001 (DATE, 2003)

Energy Estimation for Extensible Processors. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE, 2003)

Securing Mobile Appliances: New Challenges for the System Designer. - Anand Raghunathan; Srivaths Ravi 001; Sunil Hattangady; Jean-Jacques Quisquater (DATE, 2003)

On automatic generation of RTL validation test benches using circuit testing techniques. - Indradeep Ghosh; Srivaths Ravi 001 (ACM Great Lakes Symposium on VLSI, 2003)

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2003)

A Scalable Application-Specific Processor Synthesis Methodology. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2003)

Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (ICCD, 2003)

Analyzing the energy consumption of security protocols. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ISLPED, 2003)

Embedding Security in Wireless Embedded Systems. - Srivaths Ravi 001; Anand Raghunathan; Srimat T. Chakradhar (VLSI Design, 2003)

Efficient RTL Power Estimation for Large Designs. - Srivaths Ravi 001; Anand Raghunathan; Srimat T. Chakradhar (VLSI Design, 2003)

Security as a new dimension in embedded system design. - Srivaths Ravi 001; Paul C. Kocher; Ruby B. Lee; Gary McGraw; Anand Raghunathan (DAC, 2004)

High-level synthesis using computation-unit integrated memories. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2004)

Power estimation for cycle-accurate functional descriptions of hardware. - Lin Zhong 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2004)

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2004)

Tamper Resistance Mechanisms for Secure, Embedded Systems. - Srivaths Ravi 001; Anand Raghunathan; Srimat T. Chakradhar (VLSI Design, 2004)

A hybrid energy-estimation technique for extensible processors. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Custom-instruction synthesis for extensible-processor platforms. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Security in embedded systems: Design challenges. - Srivaths Ravi 001; Anand Raghunathan; Paul C. Kocher; Sunil Hattangady (ACM Trans. Embed. Comput. Syst., 2004)

SECA: security-enhanced communication architecture. - Joel Coburn; Srivaths Ravi 001; Anand Raghunathan; Srimat T. Chakradhar (CASES, 2005)

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (CICC, 2005)

Enhancing security through hardware-assisted run-time validation of program data properties. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2005)

Power emulation: a new paradigm for power estimation. - Joel Coburn; Srivaths Ravi 001; Anand Raghunathan (DAC, 2005)

Efficient fingerprint-based user authentication for embedded systems. - Pallav Gupta; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DAC, 2005)

Hybrid simulation for embedded software energy estimation. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (DAC, 2005)

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE, 2005)

Hardware Accelerated Power Estimation. - Joel Coburn; Srivaths Ravi 001; Anand Raghunathan (DATE, 2005)

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (VLSI Design, 2005)

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2005)

Generation of distributed logic-memory architectures through high-level synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Architectural support for safe software execution on embedded processors. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2006)

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (DAC, 2006)

Systematic software-based self-test for pipelined processors. - Mihalis Psarakis; Dimitris Gizopoulos; Miltiadis Hatzimihail; Antonis M. Paschalis; Anand Raghunathan; Srivaths Ravi 001 (DAC, 2006)

Architectures for efficient face authentication in embedded systems. - Najwa Aaraj; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE Designers' Forum, 2006)

Satisfiability-based framework for enabling side-channel attacks on cryptographic software. - Nachiketh R. Potlapally; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha; Ruby B. Lee (DATE Designers' Forum, 2006)

Active Learning Driven Data Acquisition for Sensor Networks. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (ISCC, 2006)

Safe Java Native Interface. - Gang Tan; Andrew W. Appel; Srimat Chakradhar; Anand Raghunathan; Srivaths Ravi 001; Daniel C. Wang (ISSSE, 2006)

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Ruby B. Lee; Niraj K. Jha (VLSI Design, 2006)

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2006)

Use of Computation-Unit Integrated Memories in High-Level Synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Application-specific heterogeneous multiprocessor synthesis using extensible processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

RTL-Aware Cycle-Accurate Functional Power Estimation. - Lin Zhong 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Mob. Comput., 2006)

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Scalable Synthesis Methodology for Application-Specific Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Energy and execution time analysis of a software-based trusted platform module. - Najwa Aaraj; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (DATE, 2007)

Methodology for low power test pattern generation using activity threshold control logic. - Srivaths Ravi 001; V. R. Devanathan; Rubin A. Parekhji (ICCAD, 2007)

Power-aware test: Challenges and solutions. - Srivaths Ravi 001 (ITC, 2007)

Tutorial T1: Designing Secure SoCs. - Srivaths Ravi 001; Stefan Mangard (VLSI Design, 2007)

Automated Energy/Performance Macromodeling of Embedded Software. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Hybrid Simulation for Energy Estimation of Embedded Software. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Energy-optimizing source code transformations for operating system-driven embedded software. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2007)

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. - Najwa Aaraj; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Architectural Support for Run-Time Validation of Program Data Properties. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. - Nachiketh R. Potlapally; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha; Ruby B. Lee (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Ruby B. Lee; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Power Analysis and Reduction Techniques for Transition Fault Testing. - Khushboo Agarwal; Srinivas Vooka; Srivaths Ravi 001; Rubin A. Parekhji; Arjun Singh Gill (ATS, 2008)

Variability-Tolerant Register-Transfer Level Synthesis. - Anish Muttreja; Srivaths Ravi 001; Niraj K. Jha (VLSI Design, 2008)

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. - Rajesh Tiwari; Abhijeet Shrivastava; Mahit Warhadpande; Srivaths Ravi 001; Rubin A. Parekhji (VTS, 2008)

Low Power Test for Nanometer System-on-Chips (SoCs). - Srivaths Ravi 001; Rubin A. Parekhji; Jayashree Saxena (J. Low Power Electron., 2008)

Systematic Software-Based Self-Test for Pipelined Processors. - Dimitris Gizopoulos; Mihalis Psarakis; Miltiadis Hatzimihail; Michail Maniatakos; Antonis M. Paschalis; Anand Raghunathan; Srivaths Ravi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. - George Kurian; Narayana Rao; Virendra Patidar; V. Kamakoti 001; Srivaths Ravi 001 (J. Low Power Electron., 2009)

Methodology for early and accurate test power estimation at RTL. - Abhay Singh; Milan Shetty; Srivaths Ravi 001; Ravindra Nibandhe (ITC, 2010)

A generic low power scan chain wrapper for designs using scan compression. - Amit Sabne; Rajesh Tiwari; Abhijeet Shrivastava; Srivaths Ravi 001; Rubin A. Parekhji (VTS, 2010)

Multi-CoDec Configurations for Low Power and High Quality Scan Test. - Arvind Jain; Sundarrajan Subramanian; Rubin A. Parekhji; Srivaths Ravi 001 (VLSI Design, 2011)

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. - Arvind Jain; Sundarrajan Subramanian; Rubin A. Parekhji; Srivaths Ravi 001 (J. Low Power Electron., 2011)

Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs. - Chandan Kumar; Fadi Maamari; Kiran Vittal; Wilson Pradeep; Rajesh Tiwari; Srivaths Ravi 001 (ATS, 2014)

At-speed capture power reduction using layout-aware granular clock gate enable controls. - Raashid Shaikh; Pradeep Wilson; Khushboo Agarwal; H. V. Sanjay; Rajesh Tiwari; Kaushik Lath; Srivaths Ravi 001 (ITC, 2014)

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. - Srivaths Ravi 001; Vivek Chickermane; Krishna Chakravadhanula (VLSID, 2014)

Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. - Prabhat Mishra 001; Swarup Bhunia; Srivaths Ravi 001 (VLSID, 2015)

Demystifying automotive safety and security for semiconductor developer. - V. Prasanth 001; David Foley; Srivaths Ravi 001 (ITC, 2017)

Foreword. - Yiorgos Makris; Srivaths Ravi 001; Amit Majumdar 002 (VTS, 2017)

Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing. - Praise O. Farayola; Shravan K. Chaganti; Abdullah O. Obaidi; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (VTS, 2020)

Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (DTIS, 2021)

An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study. - Isaac Bruce; Praise O. Farayola; Shravan K. Chaganti; Abdullah O. Obaidi; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (ETS, 2021)

Systematic Hardware Error Identification and Calibration for Massive Multisite Testing. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abdullah O. Obaidi; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (ITC, 2021)

Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing. - Praise O. Farayola; Shravan K. Chaganti; Abdullah O. Obaidi; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2021)

Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (DFT, 2022)

Graph Theory Approach for Multi-site ATE Board Parameter Extraction. - Abraham Steenhoek; Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (ETS, 2022)

Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (ITC, 2022)

The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (VTS, 2022)

A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing. - Praise O. Farayola; Isaac Bruce; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (J. Electron. Test., 2022)

A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing. - Isaac Bruce; Praise O. Farayola; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (J. Electron. Test., 2023)

Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction. - Praise O. Farayola; Ekaniyere Oko-Odion; Shravan K. Chaganti; Abalhassan Sheikh; Srivaths Ravi 001; Degang Chen 001 (IEEE Des. Test, 2023)