Hardware implementation low power high speed FFT core. - Muniandi Kannan; Srivatsa Srinivasa (Int. Arab J. Inf. Technol., 2009)

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. - Kaisheng Ma; Xueqing Li 002; Srivatsa Rangachar Srinivasa; Yongpan Liu; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ASP-DAC, 2017)

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via. - Srivatsa Rangachar Srinivasa; Karthik Mohan; Wei-Hao Chen; Kuo-Hsinag Hsu; Xueqing Li 002; Meng-Fan Chang; Sumeet Kumar Gupta; John Sampson; Vijaykrishnan Narayanan (ISVLSI, 2017)

Emerging reconfigurable nanotechnologies: can they support future electronics? - Shubham Rai; Srivatsa Rangachar Srinivasa; Patsy Cadareanu; Xunzhao Yin; Xiaobo Sharon Hu; Pierre-Emmanuel Gaillardon; Vijaykrishnan Narayanan; Akash Kumar 001 (ICCAD, 2018)

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support. - Srivatsa Rangachar Srinivasa; Akshay Krishna Ramanathan; Xueqing Li 002; Wei-Hao Chen; Fu-Kuo Hsueh; Chih-Chao Yang; Chang-Hong Shen; Jia-Min Shieh; Sumeet Kumar Gupta; Meng-Fan Marvin Chang; Swaroop Ghosh; Jack Sampson; et al. (ISLPED, 2018)

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. - Jinhang Choi; Srivatsa Rangachar Srinivasa; Yasuki Tanabe; Jack Sampson; Vijaykrishnan Narayanan (ISVLSI, 2018)

Harnessing Emerging Technology for Compute-in-Memory Support. - Nicholas Jao; Akshay Krishna Ramanathan; Srivatsa Rangachar Srinivasa; Sumitha George; John Sampson; Vijaykrishnan Narayanan (ISVLSI, 2018)

Symmetric 2-D-Memory Access to Multidimensional Data. - Sumitha George; Xueqing Li 002; Minli Julie Liao; Kaisheng Ma; Srivatsa Rangachar Srinivasa; Karthik Mohan; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. - Srivatsa Rangachar Srinivasa; Xueqing Li 002; Meng-Fan Chang; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs. - Srivatsa Rangachar Srinivasa; Wei-Hao Chen; Yung-Ning Tu; Meng-Fan Chang; Jack Sampson; Vijaykrishnan Narayanan (ISCAS, 2019)

Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration. - Suman Datta; Sourav Dutta; Benjamin Grisafe; Jeff Smith; Srivatsa Srinivasa; Huacheng Ye (IEEE Micro, 2019)

Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration. - Zhixiao Zhang; Xin Si; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Meng-Fan Chang (IEEE Micro, 2019)

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support. - Srivatsa Rangachar Srinivasa; Akshay Krishna Ramanathan; Xueqing Li 002; Wei-Hao Chen; Sumeet Kumar Gupta; Meng-Fan Chang; Swaroop Ghosh; Jack Sampson; Vijaykrishnan Narayanan (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration. - Akshay Krishna Ramanathan; Gurpreet S. Kalsi; Srivatsa Srinivasa; Tarun Makesh Chandran; Kamlesh R. Pillai; Om Ji Omer; Vijaykrishnan Narayanan; Sreenivas Subramoney (MICRO, 2020)

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. - Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Dileep Kurian; Indranil Chakraborty; Sirisha Rani Kale; Nilesh Jain; Tanay Karnik; Ravi R. Iyer 001; Anuradha Srinivasan (DATE, 2021)

CAPE: A Content-Addressable Processing Engine. - Helena Caminal; Kailin Yang; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Khalid Al-Hawaj; Tianshu Wu; Vijaykrishnan Narayanan; Christopher Batten; José F. Martínez (HPCA, 2021)

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. - Srivatsa Srinivasa; Akshay Krishna Ramanathan; Jainaveen Sundaram; Dileep Kurian; Srinivasan Gopal; Nilesh Jain; Anuradha Srinivasan; Ravi R. Iyer 001; Vijaykrishnan Narayanan; Tanay Karnik (ISQED, 2021)

Cryogenic Memory Technologies. - Shamiul Alam; Md. Shafayat Hossain; Srivatsa Rangachar Srinivasa; Ahmedullah Aziz (CoRR, 2021)

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. - Srivatsa Rangachar Srinivasa; Jainaveen Sundaram Priya; Dileep Kurian; Erika Ramirez Lozano; Satish Yada; Saransh Chhabra; Kamakhya Prasad Sahu; Paolo A. Aseron; Ronald Kalim; Anuradha Srinivasan; Tanay Karnik (ISQED, 2022)

On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. - Gauthaman Murali; Aditya Iyer 001; Lingjun Zhu; Jianming Tong; Francisco Muñoz-Martínez; Srivatsa Rangachar Srinivasa; Tanay Karnik; Tushar Krishna; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)

STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration. - Varun Darshana Parekh; Zachary Wyatt Hazenstab; Srivatsa Rangachar Srinivasa; Krishnendu Chakrabarty; Kai Ni 004; Vijaykrishnan Narayanan (CoRR, 2025)