40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. - Chua-Chin Wang; Zong-You Hou; Ssu-Wei Huang (APCCAS, 2018)

A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. - Tzung-Je Lee; Ssu-Wei Huang; Chua-Chin Wang (IEEE Trans. Circuits Syst., 2020)